TEA5768HL2FE ST-Ericsson Inc, TEA5768HL2FE Datasheet - Page 8

• Manufacturer Part Number: TEA5768HL2FE
• Description: IC FM STEREO LOW POWER 32LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of TEA5768HL2FE

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Package / Case: -
• Voltage - Supply: -
• Frequency: -
• Operating Temperature: -
• Applications: -
• Sensitivity: -
• Memory Size: -
• Data Interface: -
• Data Rate - Maximum: -
• Modulation Or Protocol: -
• Antenna Connector: -
• Current - Receiving: -
• Other names: TEA5768HLBD; TEA5768HLBD

Philips Semiconductors
7.7
Fully integrated IF filter.
7.8
The FM quadrature demodulator has an integrated
resonator to perform the phase shift of the IF signal.
7.9
The FM IF analog level voltage is converted to 4 bits digital
data and output via the I
7.10
The IF counter outputs a 7-bit count result via the I
7.11
The low-pass filtered level voltage drives the soft mute
attenuator at low RF input levels. The soft mute function
can be switched off via the I
7.12
The PLL stereo decoder is adjustment-free. The stereo
decoder can be switched to mono via the I
7.13
With a decreasing RF input level the MPX decoder blends
from stereo to mono to limit the output noise. The
continuous mono to stereo blend can also be programmed
via the I
stereo transition. Stereo Noise Cancelling (SNC) can be
switched off via the I
7.14
The audio bandwidth will be reduced with a decreasing RF
input level. The function can be switched off via the
I
7.15
Two software programmable ports (open-collector) can be
addressed via the I
The port 1 (pin SWPORT1) function can be changed with
write data byte 4 bit 0 (see Table 13). Pin SWPORT1 is
then output for the ready flag of read byte 1.
2003 Nov 06
2
C-bus.
Low-power FM stereo radio for
handheld applications
IF filter
FM demodulator
Level voltage generator and analog-to-digital
converter
IF counter
Soft mute
MPX decoder
Signal dependent mono to stereo blend
Signal dependent AF response
Software programmable ports
2
C-bus to an RF level depending switched mono to
2
C-bus.
2
C-bus.
2
C-bus.
2
C-bus.
2
C-bus.
2
C-bus.
8
8
8.1
Information about the I
“The I
9398 393 40011).
The standard I
following definitions.
IC address C0: 1100000.
Structure of the I
Subaddresses are not used.
The maximum LOW-level input and the minimum
HIGH-level input are specified to 0.2V
respectively.
The pin BUSMODE must be connected to ground.
Note: The bus operates at a maximum clock frequency of
400 kHz. It is not allowed to connect the IC to a bus
operating at a higher clock rate.
8.1.1
Data sequence: address, byte 1, byte 2, byte 3, byte 4 and
byte 5 (the data transfer has to be in this order). The
LSB = 0 of the address indicates a WRITE operation to the
TEA5768HL.
Bit 7 of each byte is considered as the MSB and has to be
transferred as the first bit of the byte.
The data becomes valid bitwise at the appropriate falling
edge of the clock. A STOP condition after any byte can
shorten transmission times.
When writing to the transceiver by using the STOP
condition before completion of the whole transfer:
The IC can be switched into a low current standby mode
with the standby bit; the bus is then still active. The
standby current can be reduced by deactivating the bus
interface (pin BUSENABLE LOW). If the bus interface is
deactivated (pin BUSENABLE LOW) without the standby
mode being programmed, the IC maintains normal
operation, but is isolated from the bus lines.
The remaining bytes will contain the old information
If the transfer of a byte is not completed, the new bits will
be used, but a new tuning cycle will not be started.
I
2
C-BUS AND BUS-CONTROLLED FUNCTIONS
2
C-bus and how to use it” (order number
I
2
C-bus specification
D
ATA TRANSFER
2
C-bus specification is expanded by the
2
C-bus logic: slave transceiver.
2
C-bus can be found in the brochure
Preliminary specification
TEA5768HL
CCD
and 0.45V
CCD