SI4703-B17-GMR Silicon Laboratories Inc, SI4703-B17-GMR Datasheet - Page 18

• Manufacturer Part Number: SI4703-B17-GMR
• Description: IC TUNER FM RADIO RDS/RBDS 20QFN
• Manufacturer: Silicon Laboratories Inc

Specifications of SI4703-B17-GMR

• Frequency: 76MHz ~ 108MHz
• Sensitivity: *
• Data Rate - Maximum: *
• Modulation Or Protocol: *
• Applications: *
• Current - Receiving: *
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Features: *
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: *
• Package / Case: 20-VQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -

Si4703-B17
When proper voltages are applied to the Si4703, the
ENABLE and DISABLE bits in register 02h can be used
to select between powerup and powerdown modes.
When voltage is first applied to the device, ENABLE = 0
and DISABLE = 0. Setting ENABLE = 1 and DISABLE
= 0 puts the device in powerup mode. To power down
the device, the ENABLE and DISABLE bits should both
be written to 1. After being written to 1, both bits will be
cleared as part of the internal device powerdown
sequence. To put the device back into powerup mode,
set ENABLE = 1 and DISABLE = 0 as described above.
The ENABLE bit should never be written to a 0.
4.10. Audio Output Summation
The audio outputs LOUT and ROUT may be
capacitively summed with another device. Setting the
audio high-Z enable (AHIZEN) bit maintains a dc bias of
0.5 x V
ESD diodes from clamping to the V
response to the output swing of the other device. The
bias point is set with a 370 k resistor to V
Register 07h containing the AHIZEN bit must not be
written during the powerup sequence and only takes
effect when in powerdown and V
powerup the LOUT and ROUT pins are set to the
common mode voltage specified in Table 7, “FM
Receiver Characteristics
the state of AHIZEN. Bits 13:0 of register 07h must be
preserved as 0x0100 while in powerdown and as
0x3C04 while in powerup.
4.11. Initialization Sequence
Refer to Figure 9, “Initialization Sequence,” on page 18.
To initialize the device:
1. Supply V
2. Supply V
3. Select 2-wire or 3-wire control interface bus mode
4. Provide RCLK. Steps 3 and 4 may be reversed when using
5. Set the ENABLE bit high and the DISABLE bit low to
To power down the device:
1. (Optional) Set the AHIZEN bit high to maintain a dc bias of
18
1 and 2 may be reversed. Power supplies may be
sequenced in any order.
operation as described in Section 4.9. "Reset, Powerup,
and Powerdown" on page 17.
an external oscillator. Wait 500 ms for oscillator startup
when using internal oscillator.
powerup the device. Software should wait for the powerup
time
Characteristics
normal part operation.
0.5 x V
powerdown, but preserve the states of the other bits in
IO
IO
on the LOUT and ROUT pins to prevent the
(as
A
IO
volts at the LOUT and ROUT pins while in
and V
while keeping the RST pin low. Note that steps
specified
1,2
D
,” on page 10) before continuing with
.
1,2
by
,” on page 10, regardless of
Table 7,
IO
IO
is supplied. In
or GND rail in
“FM
IO
and GND.
Confidential Rev. 1.0
Receiver
2. Set the ENABLE bit high and the DISABLE bit high to
3. (Optional) Remove RCLK.
4. Remove V
To power up the device (after power down):
1. Note that V
2. (Optional) Set the AHIZEN bit low to disable the dc bias of
3. Supply V
4. Provide RCLK. Wait 500 ms for oscillator startup when
5. Set the ENABLE bit high and the DISABLE bit low to
4.12. Programming Guide
Refer to "AN230: Si4700/01 Programming Guide" for
control interface programming information.
VA,VD Supply
ENABLE Bit
VIO Supply
RCLK Pin
Register 07h. Note that in powerup the LOUT and ROUT
pins are set to the common mode voltage specified in
Table 7 on page 10, regardless of the state of AHIZEN.
place the device in powerdown mode. Note that all register
states are maintained so long as V
RST pin is high.
supplied, refer to device initialization procedure above.
0.5 x V
the states of the other bits in Register 07h. Note that in
powerup the LOUT and ROUT pins are set to the common
mode voltage specified in Table 7 on page 10, regardless
of the state of AHIZEN.
using internal oscillator.
powerup the device.
RST Pin
Figure 9. Initialization Sequence
IO
1
A
volts at the LOUT and ROUT pins, but preserve
A
and V
IO
and V
is still supplied in this scenario. If V
D
2
.
D
supplies as needed.
3
IO
4
is supplied and the
5
IO
is not