MC33596FJAER2 Freescale Semiconductor, MC33596FJAER2 Datasheet - Page 41

• Manufacturer Part Number: MC33596FJAER2
• Description: IC UHF RECEIVER PLL TUNED 32LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC33596FJAER2

• Frequency: 304, 315, 426, 434, 868 & 915MHz
• Sensitivity: -104dBm
• Data Rate - Maximum: 22.4 kBaud
• Modulation Or Protocol: FSK, OOK
• Applications: General Data Transfer
• Current - Receiving: 10.3mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.7 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 32-LQFP
• Operating Temperature (min): -20C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Modulation Type: FSK/OOK
• Package Type: LQFP
• Operating Supply Voltage (min): 2.1V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

ID[5:0] (Identifier) sets the identifier. The ID is Manchester coded. Its LSB corresponds to the register’s
LSB, whatever the specified length.
Figure 31
HDL[1:0] (Header Length) sets the length of the header, as shown on
HD[5:0] (Header) sets the header. The header is Manchester coded. Its LSB corresponds to the register’s
LSB, whatever the specified length.
16.6 RSSI Register
Figure 32
Bits RSSI[7:4] contain the result of the analog-to-digital conversion of the signal measured at the LNA
output.
Freescale Semiconductor
Reset Value
Reset Value
Bit Name
Bit Name
Access
Access
defines the Header register, HEADER.
describes the RSSI Result register, RSSI.
RSSI7
HDL1
Bit 7
Bit 7
R/W
R
1
0
RSSI6
HDL0
Bit 6
Bit 6
R/W
R
0
0
HDL1
IDL1
0
0
1
1
0
0
1
1
Table 19. Header Length Selection
RSSI5
Bit 5
HD5
Bit 5
R/W
Table 18. ID Length Selection
Figure 31. HEADER Register
R
0
0
Figure 32. RSSI Register
MC33596 Data Sheet, Rev. 4
HDL0
IDL0
0
1
0
1
0
1
0
1
RSSI4
Bit 4
HD4
Bit 4
R/W
R
0
0
RSSI3
Bit 3
HD3
Bit 3
R/W
R
0
0
HD Length
ID Length
2 bits
4 bits
5 bits
6 bits
1 bits
2 bits
4 bits
6 bits
RSSI2
Bit 2
HD2
Bit 2
R/W
Table
R
0
0
19.
RSSI1
HD1
Bit 1
R/W
Bit 1
R
0
0
Register Description
RSSI0
Bit 0
HD0
R/W
Bit 0
R
0
0
Addr
Addr
$0B
$0C
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