ATA5743P3-TKSY Atmel, ATA5743P3-TKSY Datasheet - Page 15

• Manufacturer Part Number: ATA5743P3-TKSY
• Description: IC RCVR ASK/FSK 300KHZ 20SSOP
• Manufacturer: Atmel

Specifications of ATA5743P3-TKSY

• Frequency: 300MHz ~ 450MHz
• Sensitivity: -110dBm
• Data Rate - Maximum: 10 kBaud
• Modulation Or Protocol: ASK, FSK
• Applications: RKE, Telemetering, Security Technology
• Current - Receiving: 7.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SOIC (0.200", 5.30mm Width)
• Operating Frequency (max): 450000kHz
• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 4.4mm
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Figure 6-5.
Figure 6-6.
4839B–RKE–08/05
IC_ACTIVE
Bit check
Dem_out
Bit-check-
counter
(Lim_min = 14, Lim_max = 24)
IC_ACTIVE
Bit check
Dem_out
Bit-check-
counter
(Lim_min = 14, Lim_max = 24)
Timing Diagram During Bit Check
Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Start-up mode
Start-up mode
T
T
The bit-check limits are determined by means of the formula below.
T
T
Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.
Using the above formulas, Lim_min and Lim_max can be determined according to the required
T
mum edge-to-edge time t
Processing” on page
the upper limit is Lim_max = 63.
If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (N
prevent switching to receiving mode due to noise.
Figure
Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are
enabled during T
that period. When the bit check becomes active, the bit-check counter is clocked with the cycle
T
Figure 6-5
limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim
reaches Lim_max. This is illustrated in
0
Start-up
0
Start-up
Lim_min
Lim_max
Lim_min
XClk
.
6-5,
, T
= Lim_min
= (Lim_max -1)
1
1
Lim_max
2 3 4 5 6
2 3 4 5 6
shows how the bit check proceeds if the bit-check counter value CV_Lim is within the
Figure 6-6
Startup
and T
T
1
7 8 1
XClk
Bit-check mode
2
T
16. The lower limit should be set to Lim_min
. The output of the ASK/FSK demodulator (Dem_out) is undefined during
XClk
3
and
T
XClk
Bit-check
2
4 5
3
T
. The time resolution defining T
ee
1/2 Bit
Figure 6-7 on page 16
4 5
XClk
6 7 8 9
(t
DATA_L_min
6 7 8 9
Bit check failed ( CV_Lim < Lim_min )
1/2 Bit
10
11 12
10
Figure 6-7 on page
Bit-check mode
11 12 13 14
, t
T
Bit-check
DATA_H_min
15 16 17 18 1 2 3 4 5 6
Bit check ok
illustrate the bit check for the bit-check limits
Sleep mode
0
T
) is defined in the section
Sleep
Lim_min
16.
and T
1/2 Bit
7 8 9 10 11 12 13 14 15 1 2 3 4
10. The maximum value of
Lim_max
Bit check ok
is T
ATA5743
Figure 6-6
“Digital Signal
XClk
1/2 Bit
. The mini-
Bit-check
the bit
) to
15