ATR2730-TLSY Atmel, ATR2730-TLSY Datasheet - Page 6

• Manufacturer Part Number: ATR2730-TLSY
• Description: IC L-BAND DWN-CONV DAB 28SSOP
• Manufacturer: Atmel
• Series: ATR2730r

Specifications of ATR2730-TLSY

• Rf Type: DAB
• Frequency: 1.4GHz ~ 1.55GHz
• Number Of Mixers: 1
• Gain: 24dB
• Noise Figure: 10dB
• Secondary Attributes: Up/Down Converter
• Current - Supply: 50mA
• Voltage - Supply: 8 V ~ 9.35 V
• Package / Case: 28-SSOP
• Pin Count: 28
• Screening Level: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.4
3.5
3.6
3.7
6
Voltage-controlled Oscillator
Overall Properties of the Signal Path
Power Save Mode
Frequency Synthesizer
ATR2730 [Preliminary]
A voltage-controlled oscillator supplies an LO signal to the mixer. An equivalent circuit of this
oscillator is shown in
and
VREF pins. It should be noted that V
application where the oscillator is overdriven by an external oscillator. In either case, a DC path
at a low impedance must be established between the TANK and VREF pins. The output signal
of the oscillator is fed to the LO divider block of the frequency synthesizer unit which locks the
VCO’s frequency on the frequency of a reference oscillator.
typical phase-noise performance of the oscillator in locked state.
The overall gain of this circuit amounts to 24 dB, the gain-control range is about 30 dB. With a
new AGC concept in the amplifier and mixer, the ATR2730 reaches better intermodulation dis-
tances (DIM3) at higher IF-output power levels.
For VPSM > 2V (pin 1) the power consumption in the analog part (gain-controlled amplifier and
mixer and gain-controlled circuitry) is reduced by 80%. The VCO and the PLL is not influenced
by the power-down mode.
The frequency synthesizer block consists of a reference oscillator, a reference divider, an LO
divider in order to divide the frequency of the internal oscillator, a tri-state phase detector, a lock
detector, a programmable charge pump, a loop filter amplifier, a control interface, and a test
interface. The control interface is accessed by three control pins, CI, SI1 and SI2. The test inter-
face provides test signals which represent output signals of the reference and the LO divider.
The purpose of this unit is to lock the frequency f
the reference signal applied to the input pin OSCB phase-locked loop according to the following
equation:
f
where: SF = 2464,
SF
VCO
ref
Figure 11-1 on page
= SF
is the scaling factor of the reference divider according to
f
ref
/ SF
ref
Figure 10-2 on page
16), a ceramic coaxial resonator is applied to the oscillator's TANK and
ref
has to be blocked carefully.
14. In the application circuits
VCO
of the internal VCO on the frequency f
Figure 9-1 on page 13
Table 3-1
Figure 11-1
(Figure 10-3 on page 15
shows a different
4903C–DAB–03/07
shows the
ref
of