AD8343ARUZ Analog Devices Inc, AD8343ARUZ Datasheet - Page 23

• Manufacturer Part Number: AD8343ARUZ
• Description: IC MIXER ACTIVE HI-IP3 14-TSSOP
• Manufacturer: Analog Devices Inc
• Series: AD8343r

Specifications of AD8343ARUZ

• Frequency: 0Hz ~ 2.5GHz
• Rf Type: Cellular, WLAN
• Number Of Mixers: 1
• Gain: 7dB
• Noise Figure: 14dB
• Secondary Attributes: Up/Down Converter
• Current - Supply: 60mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 14-TSSOP (0.173", 4.40mm Width)
• Supply Voltage Range: 4.5V To 5.5V
• Rf Ic Case Style: TSSOP
• No. Of Pins: 14
• Operating Temperature Range: -40°C To +85°C
• Msl: MSL 1 - Unlimited
• Ic Function: IF Subsystem
• Termination Type: SMD
• Supply Voltage Min: 4.5V
• Rohs Compliant: Yes
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Filter Terminals: SMD
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

A STEP-BY-STEP APPROACH TO IMPEDANCE
MATCHING
The following discussion addresses, in detail, the matter of
establishing a differential impedance match to the AD8343.
This section specifically deals with the input match, and the
use of Side A of the evaluation board (Figure 71). An analogous
procedure is used to establish a match to the output if desired.
Circuit Setup
The AD8343 must be powered up, driven with LO; its outputs
are terminated in a manner that avoids the common-mode
stability problem, as discussed in the Input and Output Stability
Considerations section. A convenient way to deal with the
output termination is to place ferrite chokes at L3A and L4A
and omit the output matching components altogether.
It is also important to establish the means of providing bias
currents to the input pins because this network can have
unexpected loading effects and inhibit matching progress.
Establish Target Impedance
This step is necessary when the single-ended-to-differential
network (input balun) does not produce a 50 Ω output imped-
ance. In order to provide for maximum power transfer, the
input impedance of the matching network, loaded with the
AD8343 input impedance (including ballast resistors), is the
conjugate of the output impedance of the single-ended-to-
differential network. This step is of particular importance
when utilizing transmission line baluns because the differential
output impedance of the input balun can differ significantly
from what is expected. Therefore, it is a good idea to make a
separate measurement of this impedance at the desired operating
frequency before proceeding with the matching of the AD8343.
The idea is to make a differential measurement at the output of
the balun, with the single-ended port of the balun terminated
in 50 Ω. Again, there are two methods available for making this
measurement: use of the ATN multiport network analyzer to
measure the differential impedance directly, or use of a standard
two-port network analyzer and Konstroffer’s transformation
equation.
In order to utilize a standard two-port analyzer, connect the
two ports of the calibrated vector network analyzer (VNA) to
the balanced output pins of the balun, measure the two-port S
parameters, then use Konstroffer’s formula to convert the two-
port parameters to one-port differential Γ:
Γs
=
(
2
×
S11
(
−
2
S21
−
S21
)(
1
)(
−
1
S22
−
S22
−
S12
−
S12
) (
+
) (
+
1
−
1
S11
−
S11
−
S21
−
S21
)(
1
)(
+
1
S22
+
S22
−
)
2
Rev. B | Page 23 of 32
×
S12
)
Measure AD8343 Differential Impedance at Location of
First Matching Component
Once the target impedance is established, the next step in matching
to the AD8343 is to measure the differential impedance at the
location of the first matching component. The A side of the
evaluation board is designed to facilitate doing so.
Before doing the board measurements, it is necessary to perform
a full two-port calibration of the VNA at the ends of the cables
that are used to connect to the board’s input connectors, using
the SOLT (Short, Open, Load, Thru) method or equivalent. It
is a good idea to set the VNAs sweep span to a few hundred
megahertz or more for this work because it is often useful to see
what the circuit is doing over a large range of frequencies, not
just at the intended operating frequency. This is particularly
useful for detecting stability problems.
After the calibration is complete, connect Network Analyzer
Port 1 and Network Analyzer Port 2 to the differential inputs
of the AD8343 Evaluation Board.
On the AD8343 evaluation board, it is necessary to temporarily
install jumpers at Z1A and Z3A if Z4A is the desired component
location. 0 Ω resistors or capacitors of sufficient value to exhibit
negligible reactance work nicely for this purpose.
Next, extend the reference plane to the location of your first
matching component. This is accomplished by solidly shorting
both pads at the component location to GND Power to the
board must be off for this operation. Adjust the VNA reference
plane extensions to make the entire trace collapse to a point (or
best approximation thereof near the desired frequency) at the
zero impedance point of the Smith Chart. Do this for each port.
A reasonable way to provide a good RF short is to solder a piece
of thin copper or brass sheet on edge across the pads to the
nearby GND pads.
Now, remove the short, apply power to the board, and take
readings. Look at both S11 and S22 to verify that they remain
inside the unit circle of the Smith Chart over the whole frequency
range being swept. If they fail to do so, this is a sign that the
device is unstable (perhaps due to an inappropriate common-
mode load) or that the network analyzer calibration is wrong.
Either way, the problem must be addressed before proceeding
further.
Assuming that the values look reasonable, use Konstroffer’s
formula to convert to differential Γ.
Design the Matching Network
Perform a trial design of a matching network utilizing standard
impedance matching techniques. The network can be designed
using single-ended network values, and then converted to
differential form as illustrated in Figure 56. Figure 67 shows a
theoretical design of a Series C/Shunt C L-network applied
between 50 Ω and a typical load at 1.8 GHz.
AD8343