SP16130CH4RB National Semiconductor, SP16130CH4RB Datasheet
SP16130CH4RB
Specifications of SP16130CH4RB
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SP16130CH4RB Summary of contents
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... Power-down and sleep modes ■ On chip precision reference and sample-and-hold circuit ■ On chip low jitter duty-cycle stabilizer Block Diagram © 2010 National Semiconductor Corporation ADC16V130 ■ Offset binary or 2's complement data format ■ Full data rate LVDS output port ■ ...
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Connection Diagram Ordering Information ≤ Industrial (−40°C ADC16V130CISQ ADC16V130EB www.national.com ≤ T +85° 30062601 Package 64 Pin LLP Evaluation Board ...
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Pin Descriptions Pin No. Symbol Equivalent Circuit ANALOG I/O IN+ IN REF 10 CLK+ ...
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Pin No. Symbol Equivalent Circuit DIGITAL I/O D0+/- to D3+/- 15 – 22 D4+/- to D7+/- 25 – 32 D8+/- to D11+/- 35 – 42 D12+/- to D15 45 – 52 +/- 53, 54 OR+/- 33, 34 OUTCLK+/- 14 PD ...
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Pin No. Symbol Equivalent Circuit V 24 23, 43 DRGND Output Driver Power Supply. This pin should be connected to a quiet Power voltage source and be decoupled to DRGND with a 0.1μF capacitor close to the power ...
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... Absolute Maximum Ratings 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V ) A3.0 Supply Voltage ( A1.8 AD1 Voltage at any Pin except D0- D15, OVR, OUTCLK, CLK Voltage at CLK, V Pins IN Voltage at D0-D15, OR, ...
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Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply -1dBFS, LVDS Rterm = 100 Ω pF. Typical values are for T L other limits apply for T = 25°C, unless otherwise noted. A ...
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Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply -1dBFS, LVDS Rterm = 100 Ω other limits apply for T = 25°C, unless otherwise noted. A Symbol Parameter I Analog 3.0V Supply Current A3.0 ...
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Note 3: When the input voltage at any pin exceeds the power supplies (that is, V ±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ...
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Specification Definitions APERTURE DELAY is the time after the falling edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...
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Timing Diagrams Transfer Characteristic Digital Output Timing Transfer Characteristic (Offset Binary Format) 11 30062603 30062699 www.national.com ...
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Typical Performance Characteristics, DNL, INL Unless otherwise noted, these specifications apply: V Mode, Offset Binary Format. LVDS Rterm = 100 Ω. C DNL DNL vs.V www.national.com = +3.0V A3.0 A1.8 AD1 pF. Typical values are ...
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Typical Performance Characteristics, Dynamic Performance Unless otherwise noted, these specifications apply: V Mode, Offset Binary Format. LVDS Rterm = 100 Ω. C SNR, SINAD, SFDR vs. f SNR, SINAD, SFDR vs. V SNR, SINAD, SFDR vs +3.0V, V ...
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Spectral Response @ 10.11 MHz Spectral Response @ 40.11 MHz Spectral Response @ 70.11 MHz www.national.com Spectral Response @ 160.11 MHz 30062619 Spectral Response @ 240.11 MHz 30062621 Core Power vs. Temperature (Excludes I 30062623 14 30062620 30062622 ) DR ...
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Functional Description Operating on dual +1.8 and +3.0V supplies, the ADC16V130 digitizes a differential analog input signals to 16 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. The user ...
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Input Common Mode The analog inputs of the ADC16V130 are not internally dc biased and the range of input common mode is very narrow. Hence it is highly recommended to use the common mode voltage (V , typically 1.15V) ...
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A measured S11 of the input circuit of the ADC16V130 is shown in Figure 5 (Currently the figure is a simulated one subject to be changed later. Note that the simulated S11 closely matches with the measured S11). ...
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The differential receiver of the ADC16V130 has excellent low noise floor but its bandwidth is wide as multiple times of clock rate. The wide band noise folds back to nyquist frequency band in frequency domain at ADC output. Increased slope ...
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Duty Cycle Stabilizer Highest operating speed with optimal performance could be only achieved with 50% of clock duty cycle because the switched-capacitor circuit of the ADC16V130 is designed to have equal amount of settling time between each stage. The ...
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While V pin is used to set input common mode level via RM transformer, a smaller serial resistor could be placed on the signal path to isolate any switching noise interfering between ADC core and input signal. The serial resistor ...
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All ground connections should have a low inductance ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 64-Lead LLP Package Ordering Number ADC16V130CISQ NS Package Number SQA64A 22 ...
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Notes 23 www.national.com ...
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