ADL5330ACPZ-R2 Analog Devices Inc, ADL5330ACPZ-R2 Datasheet
ADL5330ACPZ-R2
Specifications of ADL5330ACPZ-R2
Related parts for ADL5330ACPZ-R2
ADL5330ACPZ-R2 Summary of contents
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FEATURES Voltage-controlled amplifier/attenuator Operating frequency 10 MHz to 3 GHz Optimized for controlling output power High linearity: OIP3 31 dBm @ 900 MHz Output noise floor: −150 dBm/Hz @ 900 MHz 50 Ω input and output impedances Single-ended or differential ...
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ADL5330 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 12 Applications..................................................................................... 13 Basic Connections ...................................................................... 13 RF Input/Output Interface ........................................................ 14 ...
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SPECIFICATIONS 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match Table 1. Parameter GENERAL Usable Frequency Range Nominal Input Impedance Nominal Output Impedance 100 MHz Gain Control ...
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ADL5330 Parameter 2200 MHz Gain Control Span Maximum Gain Minimum Gain Gain Flatness vs. Frequency Gain Control Slope Gain Control Intercept Input Compression Point Input Compression Point Output Third-Order Intercept (OIP3) 1 Output Noise Floor Noise Figure 2 Input Return ...
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ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPS1, VPS2 RF Input Power at Maximum Gain OPHI, OPLO ENBL GAIN Internal Power Dissipation θ (with Pad Soldered to Board) JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead ...
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ADL5330 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions Pin No. Mnemonic VPS1, VPS2 COM1 3, 4 INHI, INLO 7 VREF 8 IPBS 9 OPBS 11 GNLO 12, 14, ...
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TYPICAL PERFORMANCE CHARACTERISTICS –10 +25°C ERROR –20 +85°C GAIN –30 +25°C GAIN –40 –40°C GAIN –50 0 0.2 0.4 0.6 0.8 V (V) GAIN Figure 3. Gain and Gain Law Conformance vs. V over Temperature at ...
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ADL5330 40 OIP3 30 20 INPUT P1dB 10 0 –10 OUTPUT P1dB –20 –30 –40 0 0.2 0.4 0.6 0.8 V (V) GAIN Figure 9. Input Compression Point, Output Compression Point, OIP3, and Noise Floor vs. V GAIN 40 30 ...
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OIP3 (–40° OIP3 (+85°C) OIP3 (+25°C) 0 –10 –20 OP1dB (+85°C) –30 –40 OP1dB (+25°C) –50 0 0.2 0.4 0.6 0.8 1.0 V (V) GAIN Figure 15. OP1dB and OIP3 vs. Gain over Temperature at 100 ...
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ADL5330 18.5 19 19.5 20 20.5 21 21.5 22 22.5 OP1dB (dBm) Figure 21. OP1dB Distribution at 900 MHz at Maximum Gain 9.5 10 ...
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V = 0.2V GAIN 450MHz 3GHz 180 V = 1.2V GAIN 1.9GHz 210 240 270 Figure 27. Input Impedance (Differential) 0 –5 –10 –15 –20 –25 –30 –35 100 600 1100 1600 2100 FREQUENCY (MHz) Figure 28. ...
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ADL5330 THEORY OF OPERATION The ADL5330 is a high performance, voltage-controlled variable gain amplifier/attenuator for use in applications with frequencies GHz. This device is intended to serve as an output variable gain amplifier (OVGA) for applications where ...
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APPLICATIONS BASIC CONNECTIONS Figure 32 shows the basic connections for operating the ADL5330. There are two positive supplies, VPS1 and VPS2, which must be connected to the same potential. Both COM1 and COM2 (common pins) should be connected to a ...
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ADL5330 RF INPUT/OUTPUT INTERFACE The ADL5330 is primarily designed for differential signals; however, there are several configurations that can be implemented to interface the ADL5330 to single-ended applications. Figure 33 to Figure 35 show three options for differential-to-single-ended interfaces. All ...
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GAIN CONTROL INPUT When the VGA is enabled, the voltage applied to the GAIN pin sets the gain. The input impedance of the GAIN pin is 1 MΩ. The gain control voltage range is between 0 V and +1.4 V, ...
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ADL5330 RF INPUT SIGNAL DAC 220pF Figure 37. ADL5330 Operating in an Automatic Gain Control Loop in Combination with the AD8318 Figure 38 shows the transfer function of the output power vs. the VSET voltage over temperature for a 900 ...
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Figure 40 shows the response of the AGC RF output to a pulse on VSET. As VSET decreases the AGC loop responds with an RF burst. Response time and the amount of signal integration are controlled by ...
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ADL5330 WCDMA TRANSMIT APPLICATION Figure 43 shows a plot of the output spectrum of the ADL5330 transmitting a single-carrier WCDMA signal (Test Model 1-64 at 2140 MHz). The carrier power output is approximately −9.6 dBm. The gain control voltage is ...
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CDMA2000 TRANSMIT APPLICATION To test the compliance to the CDMA2000 base station standard, an 880 MHz, three-carrier CDMA2000 test model signal (forward pilot, sync, paging, and six traffic, as per 3GPP2 C.S0010-B, Table 6.5.2.1) was applied to the ADL5330. A ...
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ADL5330 EVALUATION BOARD Figure 49 shows the schematic of the ADL5330 evaluation board. The silkscreen and layout of the component and circuit sides are shown in Figure 50 through Figure 53. The board is powered by a single-supply in the ...
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VPS2 COM2 VPS2 GNLO VPS2 COM1 VPS2 OPBS ENBL IPBS GAIN VREF Figure 49. Evaluation Board Schematic Rev Page ADL5330 ...
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ADL5330 Table 5. Evaluation Board Configuration Options Components Function C10, C13, Power Supply Decoupling. The nominal supply decoupling consists of C14, R2, R4, R5, R6, R12 100 pF and 0.1 μF capacitors at each power ...
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Figure 50. Component Side Silkscreen Figure 51. Circuit Side Silkscreen Figure 52. Component Side Layout Figure 53. Circuit Side Layout Rev Page ADL5330 ...
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... Temperature Range 1, 2 ADL5330ACPZ-WP −40°C to +85°C 1 ADL5330ACPZ-REEL7 −40°C to +85°C 1 ADL5330ACPZ-R2 −40°C to +85°C ADL5330-EVAL Pb-free part waffle pack. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...