SX1441EVK Semtech, SX1441EVK Datasheet - Page 42

• Manufacturer Part Number: SX1441EVK
• Description: KIT DEV FOR SX1441
• Manufacturer: Semtech
• Series: EasyBlue™r
• Type: Bluetoothr

Specifications of SX1441EVK

• For Use With/related Products: SX1441
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Contents: -
• Other names: SX1441DVK; SX1441DVK

Personal Area Network
generated at the next counter clock pulse and the counter is loaded again with the zero value as described in
Figure 18.
When in downcount mode, the counter will start counting down from the initial load value which has been written in
the corresponding RegCntX register(s) down to the zero value. Once the counter content is equal to zero, an
interrupt is generated at the next counter clock pulse and the counter is loaded again with the load value as
described in Figure 18.
The counter must be configured (capture, PWM, cascade, up/down counting mode) before writing any target value
to RegCntX register(s). This ensures that the counter will start from the correct initial value. When counters are
cascaded, both counter registers must be written to ensure that both cascaded counters will start from the correct
initial values.
Stopping and restarting a counter in counter mode without reloading a target or load value write can generate an
unwanted interrupt if this counter has been stopped at the zero value (downcount) or at it is target value (upcount).
This interrupt has already been generated when the counter has reached the zero or the target value.
3.10.7 PWM Mode
The counters can generate PWM signals (Pulse Width Modulation) on port PB outputs PB[0] and PB[1]. The PWM
mode is selected by setting RegCntConfig1[0] or RegCntConfig1[1] bit.
When RegCntConfig1[0] is set, the PWMA or PWMAB output value overrides the value set in RegPBOut[0].
When RegCntConfig1[1]
RegPBOut[1]. The corresponding ports (0 and/or 1) of PB must be configured as digital output.
Counters in PWM mode count down or up, according to the RegCntConfig1[7:4] bit setting. No interrupts and
events are generated by the counters which are in this mode. Counters count circularly: they restart at zero or at
the maximal value (0xFF when not cascaded or 0xFFFF when cascaded) when respectively an overflow or an
underflow condition occurs.
© Semtech 2006
RegCntConfig1 (bit 4, 5, 6 or 7)
RegCntOn (bit 0, 1, 2 or 3)
RegCntConfig1
RegCntOn
clock counter X
clock counter X
write RegCntX
write RegCntX
RegCntX_w
RegCntX_w
RegCntX_r
RegCntX_r
IrqX
IrqX
XX
XX
XX
(bit 4, 5, 6 or 7)
is enabled, the PWMC or PWMCD output value overrides the value set in
XX
Figure 18 - Up and down count interrupt generation
(bit 0, 1, 2 or 3)
0
3
3
1
2
down counting
3
up counting
2
1
3
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SX1441 – Bluetooth® 1.2 SoC
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