TWR-K40X256-KIT Freescale Semiconductor, TWR-K40X256-KIT Datasheet - Page 11
![TOWER SYSTEM KIT K40X256](/photos/37/58/375861/twr-kx0n-kit_sml.jpg)
TWR-K40X256-KIT
Manufacturer Part Number
TWR-K40X256-KIT
Description
TOWER SYSTEM KIT K40X256
Manufacturer
Freescale Semiconductor
Series
Kinetisr
Type
MCUr
Specifications of TWR-K40X256-KIT
Contents
4 Boards, Documentation, DVD
Processor To Be Evaluated
K40
Data Bus Width
32 bit
Interface Type
RS-232, USB, CAN, I2C, SPI, UART
Dimensions
3.5 in x 3.5 in x 3.5 in
Operating Supply Voltage
1.71 V to 3.6 V
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - M4
Silicon Core Number
MK
Silicon Family Name
Kinetis - K40
Kit Contents
4x Brds, Cable, Docs
Rohs Compliant
Yes
For Use With/related Products
Freescale Tower System, K40X256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
2.4.2 Cortex Debug+ETM Connector
The Cortex Debug+ETM connector is a 20-pin (0.05") connector providing access to the SWD, SWV,
JTAG, cJTAG, EzPort and ETM trace (4-bit) signals available on the K40 device. The pinout and K40 pin
connections to the debug connector, J14, is shown in Table 2Table 2.
Note: Many of the trace signals connected to the debug connector are also connected elsewhere on
the TWR-K40X256. Refer to Table 6 “I/O Connectors and Pin Usage Table” and Table 7 “TWR-K40X256
Primary Connector Pinout” for more information.
2.5 Infrared Port
An infrared transmit and receive interface is implemented as shown in Figure 7 below. The CMT_IRO
pin directly drives an infrared diode. The receiver uses an infrared phototransistor connected to an on-
chip analog comparator through a low-pass filter. Internal to the K40 device, the output of the analog
comparator can be routed to a UART module for easier processing of the incoming data stream.
Pin
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
Function
VTref
TMS / SWDIO
GND
TCK / SWCLK
GND
TDO / SWO
Key
TDI
GNDDetect
nRESET
Target Power
TRACECLK
Target Power
TRACEDATA[0]
GND
TRACEDATA[1]
GND
TRACEDATA[2]
GND
TRACEDATA[3]
TWR-K40X256 Tower Module User's Manual
Table 2. Cortex Debug+ETM Connector Pinout
TWR-K40X256 Connection
3.3V MCU supply (P3V3_MCU)
PTA3/SCI0_RTS_b/FTM0_CH0/JTAG_MS/SWD_DIO
GND
PTA0/SCI0_CTS_b/FTM0_CH5/JTAG_CLK/SWD_CLK/EZP_CLK
GND
PTA2/SCI0_TX/FTM0_CH7/JTAG_DO/TRACE_SWO/EZP_DO
―
PTA1/SCI0_RX/FTM0_CH6/JTAG_DI/EZP_DI
PTA4/FTM0_CH1/MS/NMI_b/EZP_CS_b
RESET_b
5V supply (via J15)
PTA6/FTM0_CH3/FB_CLKOUT/TRACE_CLKOUT
5V supply (via J15)
PTA10/FTM2_CH0/FB_AD15/FTM2_QD_PHA/TRACE_D0
GND
PTA9/FTM1_CH1/FB_AD16/FTM1_QD_PHB/TRACE_D1
GND
PTA8/FTM1_CH0/FB_AD17/FTM1_QD_PHA/TRACE_D2
GND
PTA7/FTM0_CH4/FB_AD18/TRACE_D3
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