DS8023-KIT Maxim Integrated Products, DS8023-KIT Datasheet - Page 9

• Manufacturer Part Number: DS8023-KIT
• Description: EVALUATION KIT FOR DS8023
• Manufacturer: Maxim Integrated Products

Specifications of DS8023-KIT

• Main Purpose: Interface, Smart Card
• Utilized Ic / Part: DS8023
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 90-08023-KIT

When a card is inserted into the reader (if PRES is
active), the host microcontroller can begin an activation
sequence (start a card session) by pulling CMDVCC
low. The following events form an activation sequence
(Figure 3):
Figure 3. Activation Sequence Using RSTIN and CMDVCC
1) Host: CMDVCC is pulled low.
2) DS8023: The internal oscillator changes to high
3) DS8023: The voltage generator is started
4) DS8023: Raise V
5) DS8023: I/O, AUX1, and AUX2 are enabled
6) DS8023: The CLK signal is applied to the C3 con-
7) DS8023: RST is enabled (t
frequency (t
(between t
a controlled slope (t
the internal oscillator period (approximately 25µs).
(t
tact (t
3
= t
CMDVCC
4
RSTIN
1
I/OIN
).
CLK
V
RST
+ 4T).
I/O
CC
0
0
and t
).
_______________________________________________________________________________________
CC
1
).
2
from 0 to 5V, 3V, or 1.8V with
= t
t
0
1
5
t
1
+ 1.5 × T). T is 64 times
= t
1
+ 7T).
t
2
t
3
t
4
t
5
An alternate sequence allows the application to control
when the clock is applied to the card.
If the applied clock is not needed, set CMDVCC low
with RSTIN low. In this case, CLK starts at t
200ns after the transition on I/O, see Figure 4); after t
RSTIN can be set high to obtain an answer to request
(ATR) from an inserted smart card. Do not perform acti-
vation with RSTIN held permanently high.
= t
1) Host: Set RSTIN high.
2) Host: Set CMDVCC low.
3) Host: Set RSTIN low between t
4) DS8023: RST stays low until t
5) DS8023: RSTIN has no further effect on CLK after t
ACT
Smart Card Interface
start.
the copy of RSTIN.
5
3
, then RST becomes
ATR
and t
5
; CLK will now
3
(minimum
5
5
9
.
,