SP706SEN-L Exar Corporation, SP706SEN-L Datasheet - Page 11

• Manufacturer Part Number: SP706SEN-L
• Description: IC SUPERVISOR MPU LP 8NSOIC
• Manufacturer: Exar Corporation
• Type: Simple Reset/Power-On Resetr

Specifications of SP706SEN-L

• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Number Of Voltages Monitored: 1
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.93V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Chip Enable Signals: No
• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 1 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Output Type: Active Low
• Power Fail Detection: Yes
• Monitored Voltage: 2.93 V
• Undervoltage Threshold: 0.6 V
• Overvoltage Threshold: 3.85 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 200 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Supply Current (typ): 25 uA
• Maximum Power Dissipation: 727 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1016-1229-5

P
The power-fail comparator can be used for
various purposes because its output and non
inverting input are not internally connected.
The inverting input is internally connected to a
1.25V reference.
To build an early-warning circuit for power
failure, connect the PFI pin to a voltage divider
as shown in Figure 20. Choose the voltage
divider ratio so that the voltage at PFI falls
below 1.25V just before the +5V regulator
drops out. Use PFO to interrupt the µP so it
can prepare for an orderly power-down.
© 2010 Exar Corporation
OWER
Fig. 19: Timing Diagrams with WDI tri-stated.
-F
AIL
Fig. 20: Typical Operating Circuit
C
OMPARATOR
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M
The manual-reset input (MR) allows RESET to
be triggered by a pushbutton switch. The
switch is effectively debounced by the 140ms
minimum RESET pulse width. MR is TTL/CMOS
logic compatible, so it can be driven by an
external logic line. MR can be used to force a
watchdog timeout to generate a RESET pulse
in
connect WDO to MR.
When V
longer sinks current, it becomes an open
circuit. High-impedance CMOS logic inputs can
drift to undetermined voltages if left undriven.
If a pull-down resistor is added to the RESET
pin, any stray charge or leakage currents will
be shunted to ground, holding RESET LOW.
The resistor value is not critical. It should be
about 100KΩ, large enough not to load RESET
and small enough to pull RESET to ground.
M
U
Monitor voltages other than the unregulated
DC by connecting a voltage divider to PFI and
adjusting the ratio appropriately. If required,
add hysteresis by connecting a resistor (with a
value approximately 10 times the sum of the
two resistors in the potential divider network)
between PFI and PFO. A capacitor between PFI
and GND will reduce the power-fail circuit's
sensitivity to high-frequency noise on the line
being monitored. RESET can be used to
monitor voltages other than the +3.3V/+3.0V
V
RESET pulse when PFI drops below 1.25V.
Figure 21 shows the SP706R/S/T-SP708R/S/T
series configured to assert RESET when the
+3.3V/3.0V supply falls below the RESET
threshold, or when the +12V supply falls
below approximately 11V.
M
The power-fail comparator can also monitor a
negative supply rail, shown in Figure 22. When
the negative rail is good (a negative voltage of
large magnitude), PFO is LOW. By adding the
P
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