71M6513-IGTR/F Maxim Integrated Products, 71M6513-IGTR/F Datasheet - Page 65

• Manufacturer Part Number: 71M6513-IGTR/F
• Description: IC ENERGY METER 3PH 100-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6513-IGTR/F

• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Program Memory Size: 64 KB
• Program Memory Type: Flash
• Supply Current (max): 6.4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Name
PRE_SAMPS[1:0]
RTC_SEC[5:0]
RTC_MINI[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
RTC_DEC_SEC
RTC_INC_SEC
RTM_EN
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
SECURE
SSI_EN
SSI_10M
SSI_CKGATE
SSI_FSIZE[1:0]
SSI_FPOL
SSI_RDYEN
SSI_RDYPOL
A Maxim Integrated Products Brand
Location
[Bit(s)]
2001[7:6]
2015
2016
2017
2018
2019
201A
201B
201C[1]
201C[0]
2002[3]
2060
2061
2062
2063
SFR B2[6]
2070[7]
2070[6]
2070[5]
2070[4:3]
2070[2]
2070[1]
2070[0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Dir
W
© 2005-2011 Teridian Semiconductor Corporation
Description
Together w/ SUM_CYCLES, this value determines the number of samples in
one sum cycle between XFER interrupts for the CE.
Number of samples = PRE_SAMPS*SUM_CYCLES.
The RTC interface. These are the ‘year’, ‘month’, ‘day’, ‘hour’, ‘minute’ and
‘second’ parameters for the RTC. The RTC is set by writing to these
registers. Year 00 is defined as a leap year.
RTC time correction bits. Only one bit may be pulsed at a time. When
pulsed, causes the RTC time value to be incremented (or decremented) by
an additional second the next time the RTC_SEC register is clocked. The
pulse width may be any value. If an additional correction is desired, the
MPU must wait 2 seconds before pulsing one of the bits again.
Real Time Monitor enable. When ‘0’, the RTM output is low. This bit
enables the two wire version of RTM
Four RTM probes. Before each CE code pass, the values of these registers
are serially output on the RTM pin. The RTM registers are ignored when
RTM_EN=0.
Enables security provisions that prevent external reading of flash memory
and CE program RAM. This bit is reset on chip reset and may only be set.
Attempts to write zero are ignored.
Enables the Synchronous Serial Interface (SSI) on SEG3, SEG4, and
SEG5 pins. If SSI_RDYEN is set, SEG6 is enabled also. The pins take on the
new functions SCLK, SSDATA, SFR, and SRDY, respectively. When
SSI_EN is high and LCD_EN is low, these pins are converted to the SSI
function, regardless of LCDEN and LCD_NUM. For proper LCD operation,
SSI_EN must not be high when LCD_EN is high.
SSI clock speed: 0: 5MHz, 1: 10MHz
SSI gated clock enable. When low, the SCLK is continuous. When high, the
clock is held low when data is not being transferred.
SSI frame pulse format:
0: once at beginning of SSI sequence (whole block of data),
1: every 8 bits, 2: every 16 bits, 3: every 32 bits.
SFR pulse polarity: 0: positive, 1: negative
SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is
configured as SRDY. Otherwise, it is an LCD driver.
SRDY polarity: 0: positive, 1: negative
SEC 00 to 59
MIN
HR
DAY 01 to 07 (01=Sunday)
DATE 01 to 31
MO
YR
00-42, 01-50, 10-84, 11-100
00 to 59
00 to 23 (00=Midnight)
01 to 12
00 to 256
3-Phase Energy Meter IC
71M6513/71M6513H
DATA SHEET
SEPTEMBER 2011
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