71M6511-IGT/F Maxim Integrated Products, 71M6511-IGT/F Datasheet - Page 48

• Manufacturer Part Number: 71M6511-IGT/F
• Description: IC ENERGY METER RESIDENT 64-LQFP
• Manufacturer: Maxim Integrated Products

Specifications of 71M6511-IGT/F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 13 summarizes the timing relationships between the input MUX states, the CE_BUSY signal, and the two serial output
streams. In this example, MUX_DIV = 1 (four mux states) and FIR_LEN = 1 (3 CK32 cycles). Since FIR filter conversions
require two or three CK32 cycles, the duration of each MUX cycle is 1 + 2 * states defined by MUX_DIV if FIR_LEN = 0, and 1
+ 3 * states defined by MUX_DIV if FIR_LEN = 1. Followed by the conversions is a single CK32 cycle.
Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue running
until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the
same number of cycles. The result of each ADC conversion is inserted into the CE DRAM when the conversion is complete.
The CE code is designed to tolerate sudden changes in ADC data. The exact CK count when each ADC value is loaded into
DRAM is shown in Figure 13.
Figure 13 also shows that the two serial data streams, RTM and SSI, begin transmitting at the beginning of MUX_SYNC. RTM,
consisting of 140 CK cycles, will always finish before the next code pass starts. The SSI port begins transmitting at the same
time as RTM, but may significantly overrun the next code pass if a large block of data is required. Neither the CE nor the SSI
port will be affected by this overlap.
Figure 14, Figure 15, and Figure 16 show the RTM and SSI timing, respectively.
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ADC TIMING
CE TIMING
RTM and SSI TIMING
ADC EXECUTION
CE_EXECUTION
NOTES:
XFER_BUSY
MUX STATE
MUX_SYNC
A Maxim Integrated Products Brand
CE_BUSY
CK32
RTM
SSI
1. ALL DIMENSIONS ARE 5MHZ CK COUNTS.
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
S
0
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers
150
LAST SSI TRANSFER
0
CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 5)
© 2005–2010 Teridian Semiconductor Corporation
ADC0
ADC, CE and SERIAL TIMING
450
INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
MUX_DIV
1
Conversions (MUX_DIV=4 is shown)
ADC MUX Frame
ADC1
Single-Phase Energy Meter IC
900
71M6511/71M6511H
2
DATA SHEET
ADC2
1350
MAX CK COUNT
3
BEGIN SSI TRANSFER
NOVEMBER 2010
ADC3
1800
Settle
140
S
V2.7