71M6521DE-IM/F Maxim Integrated Products, 71M6521DE-IM/F Datasheet - Page 28
71M6521DE-IM/F
Manufacturer Part Number
71M6521DE-IM/F
Description
IC ENERGY METER 16K FLASH 68-QFN
Manufacturer
Maxim Integrated Products
Specifications of 71M6521DE-IM/F
Mounting Style
SMD/SMT
Package / Case
QFN-68
Program Memory Size
16 KB
Program Memory Type
Flash
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 24 specifies the combinations of operation modes allowed for timer 0 and timer 1:
Timer/Counter Mode Control register (PCON):
The SMOD bit in the PCON register doubles the baud rate when set.
WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset,
the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a
reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be
stopped unless the internal reset signal becomes active.
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register enters the state
0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and
requests a reset state. WDTS is cleared either by the reset signal or by changing the state of the WDT timer.
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from
becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first
instruction sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and
SWDT is 12 clock cycles. If this period has expired and SWDT has not been set, the WDT is automatically reset,
otherwise the watchdog timer is reloaded with the content of the WDTREL register and the WDT is automatically
reset. Since the WDT requires exact timing, firmware needs to be designed with special care in order to avoid
unwanted WDT resets. It is strongly discouraged to use the software WDT.
Page: 28 of 107
PCON.7
Bit
Note: It is recommended to use the hardware watchdog timer instead of the software watchdog
timer.
MSB
SMOD
Timer 0 - mode 0
Timer 0 - mode 1
Timer 0 - mode 2
Symbol
SMOD
--
Function
Baud rate control.
Table 26: PCON Register Bit Description
--
Table 25: The PCON Register
Table 24: Timer Modes
Not allowed
Mode 0
--
YES
YES
--
Not allowed
Timer 1
Mode 1
YES
YES
--
--
71M6521DE/DH/FE Data Sheet
Mode 2
YES
YES
YES
--
LSB
Rev 2
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