XR16L788IQ-F Exar Corporation, XR16L788IQ-F Datasheet
XR16L788IQ-F
Specifications of XR16L788IQ-F
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XR16L788IQ-F Summary of contents
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JULY 2008 GENERAL DESCRIPTION The XR16L7881 (788 2.97V to 5.5V with 5V tolerant inputs octal Universal Receiver and Transmitter (UART). The highly integrated device is designed for high bandwidth requirement in communication systems. The global interrupt source register ...
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... DTR1# RTS1# RI1# CD1# DSR1# CTS1# RX1 TX0 DTR0# RTS0# RI0# CD0# DSR0# CTS0# RX0 ORDERING INFORMATION ART UMBER XR16L788CQ 100-Lead QFP XR16L788IQ 100-Lead QFP XR16L788 100-QFP ACKAGE PERATING EMPERATURE 0°C to +70°C -40°C to +85°C 2 REV. 1.2.3 CTS5# RX5 VCC ...
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REV. 1.2.3 PIN DESCRIPTIONS AME IN YPE DATA BUS INTERFACE A7:A0 20-27 I D7:D0 5-12 IO IOR IOW CS INT MODEM OR SERIAL I/O INTERFACE TX0 93 O ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART AME IN YPE CD0 RI0 TX1 85 O RX1 92 I RTS1 CTS1 DTR1 DSR1 CD1# ...
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REV. 1.2 AME IN YPE TX4 64 O RX4 57 I RTS4 CTS4 DTR4 DSR4 CD4 RI4 TX5 56 O RX5 49 I RTS5# ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART AME IN YPE RX7 31 I RTS7 CTS7 DTR7 DSR7 CD7 RI7 ANCILLARY SIGNALS XTAL1 82 ...
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REV. 1.2.3 1.0 DESCRIPTION The XR16L788 (788) integrates the functions of 8 enhanced 16550 UARTs, a general purpose 16-bit timer/ counter and an on-chip oscillator. The device configuration registers include a set of four consecutive interrupt source registers that provides ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 2.4 INT# Ouput The INT# interrupt output changes according to the operating mode and enhanced features setup. and 3 summarize the operating behavior for the transmitter and receiver. T ABLE Auto RS485 ...
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REV. 1.2.3 2.6 Programmable Baud Rate Generator A single Baud Rate Generator (BRG) is provided for the transmitter and receiver, allowing independent TX/RX channel control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART Programming the Baud Rate Generator Registers DLM and DLL provides the capability of selecting the operating data rate. Table 4 shows the standard data rates available with a 14.7456 MHz crystal or ...
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REV. 1.2 IGURE RANSMITTER PERATION IN NON Data Byte 16X or 8X Clock 2.7.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 2.8.1 Receive Holding Register (RHR) - Read-Only The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface ...
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REV. 1.2.3 2.9 THR and RHR Register Locations The THR and RHR register addresses for channel 0 to channel 7 is shown in RHR for channels are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART For Trigger Table D (or programmable trigger levels), the RTS# output pin is de-asserted when the the RX FIFO level reaches the RX trigger level plus the hysteresis level and is asserted ...
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REV. 1.2.3 F 10. A RTS/DTR CTS/DSR F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts 4 ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 2.11 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 788 will ...
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REV. 1.2.3 disturbance that causes signal degradation. When the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit FIFO. The transmitter automatically de-asserts RTS# or DTR# output (HIGH) prior ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 2.15 Sleep Mode with Auto Wake-Up The 788 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All ...
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REV. 1.2.3 2.16 Internal Loopback Each UART channel provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 12 shows ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 3.0 XR16L788 REGISTERS The XR16L788 octal UART register set consists of the Device Configuration Registers that are accessible directly from the data bus for programming general operating conditions of the UARTs and ...
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REV. 1.2.3 T ABLE Bit 7 DDRESS EAD R EGISTER [A7:A0] W RITE 0x80 R INT Source UART 7 0x81 R INT 1 UART 2 bit 1 0x82 R INT 2 UART 5 bit 0 0x83 R ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 3.1.1 The Global Interrupt Source Registers The XR16L788 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1, INT2 and INT3]. The four registers are in the ...
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REV. 1.2 UART C ABLE HANNEL Bit Bit Bit P RIORITY None RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART TIMERCNTL [0] Logic zero (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the TIMERCNTL clears the interrupt. TIMERCNTL [1] Logic zero (default) stops/pauses the timer and logic one starts/re-starts ...
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REV. 1.2.3 3.1.5 RESET [7:0] (default 0x00) Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Ch-7 The 8-bit RESET register provides the software with the ability to reset the UART(s) when there is a need. Each bit is self-resetting after ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 3.1.8 REGB [7:0] (default 0x00) REGB[0]: Simultaneous write to all 8 UARTs • Logic 0 = Write to each UART configuration register individually (default). • Logic 1 = Enable simultaneous write to ...
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REV. 1.2.3 3.2 UART CHANNEL CONFIGURATION REGISTERS The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 addresses. The 8 sets of UART configuration registers are decoded using address lines ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE RHR R Bit ...
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REV. 1.2.3 T 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A3- AME RITE RXCNT R Bit RXTRG W Bit-7 1 ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART IER[0]: RHR Interrupt Enable The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger ...
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REV. 1.2.3 4.4.1 Interrupt Generation: • LSR is by any of the LSR bits and 4. • RXRDY trigger level. • RXRDY Time-out 4-char plus 12 bits delay timer. • TXRDY ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.5 FIFO Control ...
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REV. 1.2.3 T 14: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table Table-C 1 ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX ...
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REV. 1.2.3 LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable. • Logic 0 = Data registers are selected (default). • Logic 1 = Divisor latch registers are selected. 4.7 Modem Control Register (MCR) - Read/Write The MCR ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic 1, an ...
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REV. 1.2.3 MSR[0]: Delta CTS# Input Flag • Logic change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt will be ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART T 16: A RS485 H ABLE UTO ALF MSR[7] MSR[ 4.11 SCRATCH PAD REGISTER (SPR) - ...
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REV. 1.2 ABLE ELECTABLE FCTR B -3 FCTR ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART FCTR[7:6]: TX and RX FIFO Trigger Table Select These 2 bits select the transmit and receive FIFO trigger level table When table ...
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REV. 1.2.3 EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying any enhanced bits, EFR bit-4 ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 4.16 RXCNT[7:0]: Receive FIFO Level Counter - Read Only Receive FIFO level byte count from 0x00 (zero) to 0x40 (64). It gives an indication of the number of characters in the receive ...
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REV. 1.2.3 REGISTERS DLL DLM RHR THR IER FCR ISR LCR MCR LSR MSR SPR FCTR EFR TXCNT TXTRG RXCNT RXTRG XCHAR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX[ch-7:0] IRTX[ch-7:0] RTS#[ch-7:0] DTR#[ch-7:0] HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART T ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (14x20x3.0mm 100-QFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS TA ...
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REV. 1.2 16. XR16L788 VOL S C IGURE INK 0.00 0.10 0.20 F 17. XR16L788 VOH S IGURE OURCE ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART AC ELECTRICAL CHARACTERISTICS TA (-40 + WHERE APPLICABLE Symbol P ARAMETER TC1,TC2 Clock Pulse Period TOSC Crystal Frequency TECK External Clock Frequency TAS ...
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REV. 1.2 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOR# T RDV D0-D7 A0-A7 Valid Address T AS CS# IOW# D0-D7 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART B R ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART F 19 IGURE ODE OTOROLA A0-A7 T ADS CS# T RWS R/W# T RDA D0-D7 A0-A7 T ADS CS# T RWS R/W# T WDS D0- ...
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REV. 1.2 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI IGURE ECEIVE NTERRUPT IMING RX Start D0:D7 Bit INT# ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART F 22 IGURE RANSMIT NTERRUPT IMING ...
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REV. 1.2.3 PACKAGE DIMENSIONS 100 LEAD PLASTIC QUAD FLAT P 81 100 A2 A Seating Plane A1 SYMBOL α Note: The control dimension is the ...
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... Corrected decription of Xon/Xoff/Special character interrupt. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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REV. 1.2.3 GENERAL DESCRIPTION ............................................................................................... 1 A ........................................................................................................................................... 1 PPLICATIONS F ................................................................................................................................................ 1 EATURES ............................................................................................................................................................. 1 IGURE LOCK IAGRAM ................................................................................................................................................. 2 IGURE THE EVICE ........................................................................................................................... 2 ORDERING INFORMATION ...
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XR16L788 HIGH PERFORMANCE 2.97V TO 5.5V OCTAL UART 4.4 INTERRUPT STATUS REGISTER (ISR) - READ ONLY .................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE ONLY ........................................................................................ 32 T 14: ...