XR16L2750IM-F Exar Corporation, XR16L2750IM-F Datasheet - Page 27

• Manufacturer Part Number: XR16L2750IM-F
• Description: IC UART FIFO 64B DUAL 48TQFP
• Manufacturer: Exar Corporation
• Type: IrDA or RS- 485r

Specifications of XR16L2750IM-F

• Number Of Channels: 2, DUART
• Package / Case: 48-TQFP
• Features: *
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.25 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 6.25 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: TQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1280

xr
REV. 1.2.1
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See
•
•
4.6
T
Table-C
Table-D
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
T
RIGGER
ABLE
Line Control Register (LCR) - Read/Write
FCTR
B
IT
1
1
-5
T
ABLE
FCTR
B
Table 11
IT
0
1
10: T
-4
BIT-2
RANSMIT AND
B
FCR
0
1
1
for parity selection summary below.
IT
X
0
0
1
1
-7
BIT-1
0
0
1
1
B
FCR
IT
X
0
1
0
1
W
-6
ORD LENGTH
R
5,6,7,8
6,7,8
ECEIVE
5
B
FCR
BIT-0
IT
X
0
0
1
1
0
1
0
1
-5
FIFO T
BIT
FCR
27
X
0
1
0
1
-4
RIGGER
T
Programmable
FCTR[7] = 0.
RIGGER
W
S
R
via TRG
register.
5 (default)
ORD LENGTH
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
TOP BIT LENGTH
(B
ECEIVE
T
1 (default)
16
56
60
8
ABLE AND
IT TIME
6
7
8
1-1/2
L
EVEL
2
(
S
))
Programmable
FCTR[7] = 1.
L
T
EVEL
T
register.
via TRG
RANSMIT
L
RIGGER
EVEL
16
32
56
8
S
ELECTION
16C654
16L2752, 16C2850,
16C2852, 16C850,
16C854, 16C864
C
OMPATIBILITY
XR16L2750