XR16C854IV-F Exar Corporation, XR16C854IV-F Datasheet - Page 16

• Manufacturer Part Number: XR16C854IV-F
• Description: IC UART FIFO 128B QUAD 64LQFP
• Manufacturer: Exar Corporation
• Type: Quad UART with 128-byte FIFOsr

Specifications of XR16C854IV-F

• Number Of Channels: 4, QUART
• Package / Case: 64-LQFP
• Features: *
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 2 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA to 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 45 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.97 V to 5.5 V
• No. Of Channels: 4
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1276

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 128 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
N
F
F
2.12.1
OTE
IGURE
IGURE
: Table-B selected as Trigger Table for
Receive Data
Byte and Errors
9. R
10. R
128 bytes by 11-bit
Receive Holding Register (RHR) - Read-Only
16X Clock
ECEIVER
wide FIFO
ECEIVER
16X Clock
and Errors
Data Byte
O
Receive
O
PERATION IN NON
PERATION IN
Receive Data Shift
Register (RSR)
Data FIFO
LSR bits
Receive
FIFO
Receive
Tags in
Error
Data
4:2
-FIFO M
Figure 10
Receive Data Shift
AND
Register (RSR)
Holding Register
Receive Data
A
ODE
UTO
Validation
Data falls to
Data Bit
Data fills to
(RHR)
Trigger=16
(Table
Example
FIFO
24
RTS F
8
16
: - RX FIFO trigger level selected at 16
11).
LOW
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
Validation
(See Note Below)
Data Bit
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
C
bytes
ONTROL
RHR Interrupt (ISR bit-2)
M
Receive Data Characters
ODE
Receive Data Characters
RXFIFO1
xr
RXFIFO1
REV. 3.0.1