ST16C2550CJ44-F Exar Corporation, ST16C2550CJ44-F Datasheet - Page 17

• Manufacturer Part Number: ST16C2550CJ44-F
• Description: IC DUART FIFO 16B 44PLCC
• Manufacturer: Exar Corporation
• Type: RS- 232 or RS- 485r

Specifications of ST16C2550CJ44-F

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: *
• Fifo's: 16 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.97 V ~ 5.5 V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 4 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• No. Of Channels: 2
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1254-5

REV. 4.4.1
.
See “Receiver” on page 13.
See “Transmitter” on page 12.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
N
MCR
RHR
MSR
DLM
THR
FCR
LCR
SPR
R
LSR
DLL
IER
ISR
AME
EG
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
W
R
WR
WR
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
Enabled
Trigger
Enable
Global
FIFOs
B
Error
Input
T
Bit-7
Bit-7
CD#
Bit-7
Bit-7
Bit-7
IT
ABLE
0
0
-7
7: INTERNAL REGISTERS DESCRIPTION
RX FIFO
Enabled
Trigger
Set TX
THR &
FIFOs
Empty
Break
B
Input
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
TSR
RI#
IT
0
0
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
Set Par-
Empty
DSR#
B
Input
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
IT
ity
0
0
0
0
-5
17
Internal
Enable
Break
Parity
Loop-
CTS#
B
Even
Input
Bit-4
Bit-4
back
Bit-4
Bit-4
Bit-4
RX
IT
0
0
0
-4
2.97V TO 5.5V DUART WITH 16-BYTE FIFO
Modem
Source
Enable
Enable
Enable
Output
Enable
OP2#/
Fram-
Mode
Parity
B
Delta
DMA
Error
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Stat.
CD#
INT
INT
Int.
RX
ing
IT
-3
RX Line
Source
(OP1#)
Enable
Reset
Rsrvd
Parity
B
Delta
FIFO
Error
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Stat.
Stop
Bits
INT
RI#
Int.
RX
TX
IT
-2
Control
Enable
Source
Length
Output
Empty
DSR#
Reset
RTS#
Over-
Word
B
FIFO
Error
Delta
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
RX
RX
run
TX
Int
IT
-1
Control
Enable
Source
Enable
Length
Output
Ready
FIFOs
DTR#
CTS#
B
Word
Delta
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
IT
-0
ST16C2550
LCR[7] = 0
LCR[7] = 1
C
OMMENT