MCF5251VM140 Freescale Semiconductor, MCF5251VM140 Datasheet - Page 5

• Manufacturer Part Number: MCF5251VM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5251VM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: ATA, Audio, CAN, EBI/EMI, I²C, IDE, MMC/SD, SPI, UART/USART, USB OTG
• Peripherals: DMA
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 70°C
• Package / Case: 225-MAPBGA
• Embedded Interface Type: I2C, SPI, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 225
• Operating Temperature Range: -20°C To +70°C
• Frequency Typ: 140MHz
• Rohs Compliant: Yes
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -20C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor
GPIO
GPT
IDE
INC
I
SRAM
LIN
JTAG
QSPI
RTC
BDM
SDRAMC
SIM
PLL
Mnemonic
2
C
Block
General Purpose I/O
Interface
General Timer
Module
Integrated Drive
Electronics
Instruction Cache
Inter IC
Communication
Module
Internal 128-KB
SRAM
Internal Voltage
Regulator
Joint Test Action
Group
Queued Serial
Peripheral Interface
Real-Time Clock
Background Debug
Interface
Synchronous DRAM
Memory Controller
System Integration
Module
System Oscillator and
Phase Lock Loop
Block Name
MCF5251 ColdFire Processor Data Sheet: Technical Data, Rev. 3
Table 2. Digital and Analog Modules (continued)
System
integration
Timer
peripheral
Connectivity
peripheral
Core
Connectivity
peripheral
Internal
memory
Linear
regulator
Test and
debug
Connectivity
Interface
Timer
Peripheral
Test and
debug
Peripheral
Interface
System
Integration
System
Clocking
Functional
Grouping
GPIO signals are multiplexed with various other signals.
The timer module includes two general-purpose timers, each of which
contains a free-running 16-bit timer.
The IDE hardware consists of bus buffers for address and data and are
intended to reduce the load on the bus and prevent SDRAM and Flash
accesses from propagating to the IDE bus.
The instruction cache improves system performance by providing cached
instructions to the execution unit in a single clock cycle.
The two-wire I
standard, are bidirectional serial buses that exchange data between
devices.
The 128-Kbyte on-chip SRAM is split over two banks, SRAM0 (64K) and
SRAM1 (64K). It provides single clock-cycle access for the ColdFire core.
An internal 1.2 V regulator is used to supply the CPU and PLL sections of
the MCF5251, reducing the number of external components required and
allowing operation from a single supply rail, typically 3.3 volts.
To help with system diagnostics and manufacturing testing, the MCF5251
includes dedicated user-accessible test logic that complies with the IEEE
1149.1A standard for boundary scan testability, often referred to as Joint
Test Action Group, or JTAG.
The QSPI module provides a serial peripheral interface with queued
transfer capability.
The RTC is a clock that keeps track of the current time even if the clock is
turned off.
A background-debug mode (BDM) interface provides system debug.
The SDRAM controller provides a glueless interface for one bank of
SDRAM, and can address up to 32MB. The controller supports a 16-bit
data bus. The controller operates in page mode, non-page mode, and
burst-page mode and supports SDRAMs.
The SIM provides overall control of the internal and external buses and
serves as the interface between the ColdFire core and the internal
peripherals or external devices. The SIM is responsible for the two
interrupt controllers (setting priorities and levels). And it also configures
the GPIO ports.
The oscillator operates from an external crystal connected across CRIN
and CROUT. The circuit can also operate from an external clock
connected to CRIN. The on-chip programmable PLL, which generates the
processor clock, allows the use of almost any low frequency external clock
(5–35 MHz).
2
C bus interfaces, compliant with the Philips I
Brief Description
Functional Description
2
C bus
5