DSP56F807VF80 Freescale Semiconductor, DSP56F807VF80 Datasheet - Page 11

• Manufacturer Part Number: DSP56F807VF80
• Description: IC DSP 80MHZ 60K FLASH 160-BGA
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxr

Specifications of DSP56F807VF80

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 136KB (68K x 16)
• Program Memory Type: FLASH
• Ram Size: 6K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 160-MAPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Freescale Semiconductor
No. of
No. of
Pins
Pins
1
1
1
6
2
8
GPIOE2-
GPIOA0-
GPIOE3
A8–A15
GPIOA7
EXTAL
Signal
Name
CLKO
Signal
A0–A5
A6–A7
XTAL
Name
Signal
Output
Output
Input/
Type
Input/O
Input/O
Input
Signal
Output
Output
Output
Type
utput
utput
State During
Chip-driven
Chip-driven
State During
56F807 Technical Data Technical Data, Rev. 16
Reset
Tri-stated
Tri-stated
Tri-stated
Input
Reset
Input
Input
Table 2-6 Address Bus Signals
Table 2-5 PLL and Clock
External Crystal Oscillator Input—This input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to
Crystal Oscillator Output—This output should be connected to an
8MHz external crystal or ceramic resonator. For more information, please
refer to
This pin can also be connected to an external clock source. For more
information, please refer to
Clock Output—This pin outputs a buffered clock signal. By programming
the CLKOSEL[4:0] bits in the CLKO Select Register (CLKOSR), the user
can select between outputting a version of the signal applied to XTAL and
a version of the device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
Address Bus—A0–A5 specify the address for external Program or
Data memory accesses.
Address Bus—A6–A7 specify the address for external Program or
Data memory accesses.
Port E GPIO—These two General Purpose I/O (GPIO) pins can
individually be programmed as input or output pins.
After reset, the default state is Address Bus.
Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is Address Bus.
Section
Section
3.4.
3.4.
Signal Description
Section
Signal Description
3.4.2.
Clock and Phase Locked Loop Signals
11