MC9328MXLVM20R2 Freescale Semiconductor, MC9328MXLVM20R2 Datasheet - Page 58

• Manufacturer Part Number: MC9328MXLVM20R2
• Description: IC MCU I.MX 200MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MXLr

Specifications of MC9328MXLVM20R2

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, I²C, Memory Stick, MMC/SD, SPI, SSI, UART/USART, USB
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 1.7 V ~ 3.3 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 256-MAPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -

Functional Description and Application Information
4.7
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the
MMC/SD module (inner system) and the application (user programming).
58
Note:
Symbol
T10
T10
T8
T9
T9
•
•
•
•
•
•
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In
are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period.
In
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
SCLK to valid LD data
End of HSYN idle2 to VSYN edge
(for non-display region)
End of HSYN idle2 to VSYN edge
(for Display region)
VSYN to OE active (Sharp = 0) when VWAIT2 = 0
VSYN to OE active (Sharp = 1) when VWAIT2 = 0
Multimedia Card/Secure Digital Host Controller
Figure
CMD_DAT Output
41, SCLK is always active.
CMD_DAT Input
Table 21. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing (Continued)
Bus Clock
Description
Figure 42. Chip-Select Read Cycle Timing Diagram
5a
Valid Data
MC9328MXL Technical Data, Rev. 8
4a
3a
3b
6a
Valid Data
Minimum
-3
2
1
1
2
7
1
Corresponding Register Value
2
Valid Data
Valid Data
6b
5b
3
2
1
1
2
Figure
4b
Freescale Semiconductor
41, all 3 signals
Unit
ns
Ts
Ts
Ts
Ts