MCF5253CVM140 Freescale Semiconductor, MCF5253CVM140 Datasheet - Page 17

• Manufacturer Part Number: MCF5253CVM140
• Description: IC MPU 32BIT 140MHZ 225-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF525xr

Specifications of MCF5253CVM140

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 140MHz
• Connectivity: CAN, EBI/EMI, I²C, QSPI, UART/USART, USB OTG
• Peripherals: DMA, WDT
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 225-MAPBGA
• Family Name: MCF5xxx
• Device Core: ColdFire V2
• Device Core Size: 32b
• Frequency (max): 140MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2/3.3V
• Operating Supply Voltage (max): 1.32/3.6V
• Operating Supply Voltage (min): 1.08/3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 225
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Compliant

1
2
4.2
The Sony/Philips Digital Interface (SPDIF) timing parameters are provided in
totally asynchronous, therefore there is no need for relationship with the clock.
differences between high-low and low-high propagation delay which is called the skew.
4.3
The Serial Audio Interface fully complies with the Industry standard Philips IIS (InterIC Serial Audio Bus)
timings.
4.4
Table 15
Freescale Semiconductor
EBUIN1, EBUIN2, EBUIN3, EBUIN4:
asynchronous inputs, no specs apply
EBUOUT1, EBUOUT2 output
EBUOUT1, EBUOUT2 output
PSTCLK clock rise edge to DDATA/PSTDATA
PSTCLK clock rise edge to DDATA/PSTDATA
Skew value does not include the skew introduced by different rise and fall times.
Transition times between 10% Vdd and 90% Vdd.
provides the timing parameters.
SPDIF Timing
Serial Audio Interface Timing
DDATA/PST/PSTCLK Debug Interface
Characteristic
D1
D2
D3
D4
D5
ID
Propagation delay BCLK rising to data valid
Propagation delay BCLK rising to BCLKE, SDLDQM,
SDUDQM, SDWE, SDCS0, SDRAS, SDCAS valid
Hold time BCLK rising to data valid
Propagation delay BCLK rising to A[24:9] valid
Set-up time data valid to BCLK rising
Table 15. DDATA/PST/PSTCLK Debug Interface Timing Parameters
Characteristic
Table 14. SPDIF Propagation Skew and Transition Parameters
MCF5253 ColdFire Processor Data Sheet: Technical Data, Rev. 4
Table 13. SDRAM Bus Timing Parameters
Pin Load
Characteristic
40 pF
20 pF
–
1
2
invalid
valid
Prop Delay
Maximum
–
–
–
Pin Load
Maximum
15 pF
15 pF
Skew
0.7
1.5
1.5
1
30 pF
Load
7.88
Timing to 50% Points
8.7
0.7
8.3
0
Transition
–1.0
Min
Maximum
—
Maximum
40 pF
Load
24.2
13.6
8.8
9.2
0.7
–
0
–
2
Rise
Table
Table 14
50 pF
Load
9.6
0.7
–
–
0
Electrical Specifications
Max
4.0
14. SPDIF timing is
—
Transition Fall
Maximum
Units
shows the
ns
ns
ns
ns
ns
31.3
18.0
–
Units
ns
ns
Units
ns
ns
ns
17