CY8C3246PVA-141 Cypress Semiconductor Corp, CY8C3246PVA-141 Datasheet - Page 39

• Manufacturer Part Number: CY8C3246PVA-141
• Description: IC MCU 8BIT 64KB FLASH 48SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C32xxr

Specifications of CY8C3246PVA-141

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: CapSense, DMA, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x12b, D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4.8 Analog Connections
These connections apply only to GPIO pins. All GPIO pins may
be used as analog inputs or outputs. The analog voltage present
on the pin must not exceed the V
the GPIO belongs. Each GPIO may connect to one of the analog
global busses or to one of the analog mux buses to connect any
pin to any internal analog resource such as ADC or comparators.
In addition, one select pin provides direct connection to the high
current DAC.
6.4.9 CapSense
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders. See the
“CapSense”
6.4.10 LCD Segment Drive
This section applies only to GPIO pins. All GPIO pins may be
used to generate Segment and Common drive signals for direct
glass drive of LCD glass. See the
page 57 for details.
6.4.11 Adjustable Output Level
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
external signals that are lower in voltage than the SIO’s
respective V
either the standard V
based on an internally generated reference. Typically the voltage
DAC (VDAC) is used to generate the reference (see
6-12). The
use and reference routing to the SIO pins. Resistive pull-up and
pull-down drive modes are not available with SIO in regulated
output mode.
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from V
reference sets the pins voltage threshold for a high logic level
(see
Typically the voltage DAC (VDAC) generates the V
reference. The
VDAC use and reference routing to the SIO pins.
Document Number: 001-56955 Rev. *J
0.5 × Vddio
0.4 × Vddio
0.5 × V
V
REF
Figure
REF
“DAC”
6-12). Available input thresholds are:
DDIO
section on page 57 for more information.
“DAC”
. SIO pins are individually configurable to output
section on page 58 has more details on VDAC
DDIO
section on page 58 has more details on
level or the regulated output, which is
DDIO
“LCD Direct Drive”
supply voltage to which
REF
section on
Figure
DDIO
. The
Figure 6-12. SIO Reference for Input and Output
6.4.13 SIO as Comparator
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the
section can be used to construct a comparator. The threshold for
the comparator is provided by the SIO's reference generator. The
reference generator has the option to set the analog signal
routed through the analog global line as threshold for the
comparator. Note that a pair of SIO pins share the same
threshold.
The digital input path in
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
6.4.14 Hot Swap
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a GPIO pin’s
protection diode.
Input Path
Output Path
Output
Digital
Digital
Input
SIO_Ref
PSoC
Drive
Logic
Figure 6-9
Reference
Generator
®
Driver
Vhigh
3: CY8C32 Family
Voutref
Vinref
on page 36 illustrates this
Adjustable Input Level
Data Sheet
Page 39 of 119
PIN
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