PIC18F4420-E/ML Microchip Technology, PIC18F4420-E/ML Datasheet - Page 262
PIC18F4420-E/ML
Manufacturer Part Number
PIC18F4420-E/ML
Description
IC MCU FLASH 8KX16 44QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2420-IML.pdf
(412 pages)
3.PIC18F2420-IML.pdf
(16 pages)
4.PIC18F2420-IML.pdf
(8 pages)
5.PIC18F2420-IML.pdf
(6 pages)
6.PIC18F2420-IML.pdf
(8 pages)
7.PIC18F2420-IML.pdf
(4 pages)
Specifications of PIC18F4420-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PIC18F2420/2520/4420/4520
23.3
The Two-Speed Start-up feature helps to minimize the
latency period from oscillator start-up to code execution
by allowing the microcontroller to use the INTOSC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is LP, XT, HS or HSPLL
(Crystal-Based modes). Other sources do not require
an OST start-up delay; for these, Two-Speed Start-up
should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the
internal oscillator block as the clock source, following
the time-out of the Power-up Timer after a Power-on
Reset is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
To use a higher clock speed on wake-up, the INTOSC
or postscaler clock sources can be selected to provide
a higher clock speed by setting bits, IRCF<2:0>,
immediately after Reset. For wake-ups from Sleep, the
INTOSC or postscaler clock sources can be selected
by setting the IRCF<2:0> bits prior to entering Sleep
mode.
FIGURE 23-2:
DS39631E-page 260
Two-Speed Start-up
Note 1: T
Multiplexer
CPU Clock
PLL Clock
Peripheral
Program
INTOSC
Counter
Output
OSC1
Clock
2: Clock transition typically occurs within 2-4 T
Wake from Interrupt Event
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
OST
PC
= 1024 T
Q1
OSC
T
OST (1)
; T
PLL
Q2
PC + 2
= 2 ms (approx). These intervals are not shown to scale.
T
PLL (1)
OSTS bit Set
Q3
Q4
OSC
In all other power-managed modes, Two-Speed Start-
up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
23.3.1
While using the INTOSC oscillator in Two-Speed Start-
up, the device still obeys the normal command
sequences
including
Section 3.1.4 “Multiple Sleep Commands”). In
practice, this means that user code can change the
SCS<1:0> bit settings or issue SLEEP instructions
before the OST times out. This would allow an
application
“housekeeping” tasks and return to Sleep before the
device starts to operate from the primary oscillator.
User code can also check if the primary clock source is
currently providing the device clocking by checking the
status of the OSTS bit (OSCCON<3>). If the bit is set,
the primary oscillator is providing the clock. Otherwise,
the internal oscillator block is providing the clock during
wake-up from Reset or Sleep mode.
Q1
1
.
Transition
2
Clock
n-1 n
(2)
multiple
SPECIAL CONSIDERATIONS FOR
USING TWO-SPEED START-UP
PC + 4
for
to
briefly
entering
Q2
SLEEP
Q3 Q4
© 2008 Microchip Technology Inc.
wake-up,
power-managed
instructions
Q1
PC + 6
Q2
perform
Q3
(refer
modes,
routine
to
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