ATMEGA32M1-MU Atmel, ATMEGA32M1-MU Datasheet - Page 145

• Manufacturer Part Number: ATMEGA32M1-MU
• Description: MPU AVR 32K FLASH 20MHZ 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA32M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

17.12 Analog Synchronization
17.13 Interrupt Handling
17.14 PSC Clock Sources
8209D–AVR–11/10
Each PSC module generates a signal to synchronize the ADC sample and hold; synchronisation
is mandatory for measurements.
This signal can be selected between all falling or rising edge of PSCOUTnA or PSCOUTnB
outputs.
In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchroniza-
tion of the ADC. It this case, it’s minimum value is 1.
As each PSC module can be dedicated for one function, each PSC has its own interrupt system.
List of interrupt sources:
Each PSC has two clock inputs:
Figure 17-15. Clock selection
PCLKSELn bit in PSC Control Register (PCTL) is used to select the clock source.
PPREn1/0 bits in PSC Control Register (PCTL) are used to select the divide factor of the clock.
Table 17-6.
PCLKSELn
0
0
0
• Counter reload (end of On Time 1)
• PSC Input event (active edge or at the beginning of level configured event)
• PSC Mutual Synchronization Error
• CLK PLL from the PLL
• CLK I/O
CLK
CLK
Output Clock versus Selection and Prescaler
PLL
I/O
PPREn1
0
0
1
PCLKSEL
1
0
PPREn0
0
1
0
CK
ATmega16M1/32M1/64M1
PRESCALER
CLKPSCn output
CLK I/O
CLK I/O / 4
CLK I/O / 32
CLK
PSCn
PPREn1/0
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