PIC18F2510-E/SP Microchip Technology, PIC18F2510-E/SP Datasheet - Page 64
![IC MCU FLASH 16KX16 28-DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC18F2510-E/SP
Manufacturer Part Number
PIC18F2510-E/SP
Description
IC MCU FLASH 16KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18LF2410-ISO.pdf
(376 pages)
4.PIC18LF2410-ISO.pdf
(8 pages)
5.PIC18LF2410-ISO.pdf
(16 pages)
6.PIC18LF2410-ISO.pdf
(6 pages)
7.PIC18LF2410-ISO.pdf
(6 pages)
8.PIC18LF2410-ISO.pdf
(8 pages)
Specifications of PIC18F2510-E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
For Use With
DVA18XP280 - DEVICE ADAPTER 18F2220 PDIP 28LD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18LF2410-ISO PDF datasheet #3
- PIC18LF2410-ISO PDF datasheet #4
- PIC18LF2410-ISO PDF datasheet #5
- PIC18LF2410-ISO PDF datasheet #6
- PIC18LF2410-ISO PDF datasheet #7
- PIC18LF2410-ISO PDF datasheet #8
- Current page: 64 of 376
- Download datasheet (7Mb)
PIC18F2X1X/4X1X
5.3.4
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM. SFRs start at the top of
data memory (FFFh) and extend downward to occupy
the top half of Bank 15 (F80h to FFFh). A list of these
registers is given in Table 5-1 and Table 5-2.
TABLE 5-1:
DS39636D-page 66
Note 1:
Address
FEDh POSTDEC0
FECh
FFDh
FFCh
FEEh POSTINC0
FEBh
FEAh
FFEh
FFBh
FEFh
2:
3:
FFFh
FFAh
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
FE9h
FE8h
FE7h
FE6h POSTINC1
FE5h POSTDEC1
FE4h
FE3h
FE2h
FE1h
FE0h
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is not available on 28-pin devices.
SPECIAL FUNCTION REGISTERS
PREINC0
PREINC1
PLUSW0
PLUSW1
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INDF0
INDF1
INTCON
TABLAT
PRODH
PRODL
FSR0H
FSR1H
FSR0L
WREG
FSR1L
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2X1X/4X1X DEVICES
Name
TOSU
TOSH
TOSL
BSR
PCL
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Address
FDDh POSTDEC2
FDCh
FCDh
FCCh
FDEh POSTINC2
FDBh
FDAh
FCEh
FCBh
FCAh
FDFh
FCFh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PREINC2
PLUSW2
HLVDCON
SSPCON1
SSPCON2
WDTCON
OSCCON
SSPSTAT
ADRESH
ADCON0
ADCON1
ADCON2
SSPBUF
SSPADD
ADRESL
INDF2
STATUS
TMR0H
TMR1H
FSR2H
TMR0L
T0CON
TMR1L
T1CON
T2CON
FSR2L
RCON
Name
TMR2
—
PR2
(2)
(1)
(1)
(1)
(1)
(1)
Address
The SFRs can be classified into two sets: those asso-
ciated with the “core” device functionality (ALU, Resets
and interrupts) and those related to the peripheral func-
tions. The reset and interrupt registers are described in
their respective chapters, while the ALU’s STATUS reg-
ister is described later in this section. Registers related
to the operation of a peripheral feature are described in
the chapter for that peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
FBDh
FBCh
FBEh
FBBh
FBAh
FAEh
FADh
FACh
FAAh
FBFh
FB9h
FB8h
FB7h PWM1CON
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FABh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
ECCP1AS
BAUDCON
CCP1CON
CCP2CON
CVRCON
SPBRGH
CCPR1H
CCPR2H
CCPR1L
CCPR2L
CMCON
RCREG
TMR3H
T3CON
SPBRG
TXREG
RCSTA
TMR3L
TXSTA
Name
IPR2
PIR2
PIE2
—
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
© 2009 Microchip Technology Inc.
Address
F9Dh
F9Ch
F8Dh
F8Ch
F9Eh
F9Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F8Fh
F99h
F98h
F97h
F96h
F95h
F94h
F93h
F92h
F91h
F90h
F89h
F88h
F87h
F86h
F85h
F84h
F83h
F82h
F81h
F80h
OSCTUNE
PORTD
PORTE
TRISE
TRISD
LATE
LATD
PORTC
PORTB
PORTA
TRISC
TRISB
TRISA
Name
LATC
LATB
LATA
IPR1
PIR1
PIE1
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
(3)
(3)
(3)
(3)
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