DSP56311VF150R2 Freescale Semiconductor, DSP56311VF150R2 Datasheet - Page 43

• Manufacturer Part Number: DSP56311VF150R2
• Description: IC DSP 24BIT 150MHZ 196-BGA
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56311VF150R2

• Interface: Host Interface, SSI, SCI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (576 B)
• On-chip Ram: 384kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.80V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 196-MAPBGA
• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 384KB
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (min): 1.7/1.7/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

2.4.5.3 Asynchronous Bus Arbitration Timings
The asynchronous bus arbitration is enabled by internal synchronization circuits on
synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this
delay, a DSP56300 part may assume mastership and assert
reason for timing 250.
Once
DSP56300 components that are potential masters on the same bus. If
is asserted and
Therefore, some non-overlap period between one
ensures that overlaps are avoided.
Freescale Semiconductor
250
251
Notes:
No.
BB
BB assertion window from BG input deassertion.
Delay from BB assertion to BG assertion
1.
2.
3.
is asserted, there is a synchronization delay from
Bit 13 in the Operating Mode Register must be set to enable Asynchronous Arbitration mode.
At 150 MHz, Asynchronous Arbitration mode is recommended.
To guarantee timings 250 and 251, it is recommended that you assert non-overlapping BG inputs to different DSP56300
devices (on the same bus), as shown in Figure 2-19, where BG1 is the BG signal for one DSP56300 device while BG2 is the
BG signal for a second DSP56300 device.
BB
is deasserted, another DSP56300 component may assume mastership at the same time.
BG1
BB
BG2
Figure 2-19.
Characteristics
Table 2-13.
DSP56311 Technical Data, Rev. 8
Asynchronous Bus Arbitration Timing
BG
Asynchronous Bus Timings
input active to another
BB
BB
250
assertion to the time this assertion is exposed to other
, for some time after
250+251
BG
input is asserted before that time, and
BG
251
Expression
2.5 × Tc + 5
2 × Tc + 5
input active is required. Timing 251
BG
BG
is deasserted. This is the
AC Electrical Characteristics
and
BB
Min
18.3
inputs. These
—
150 MHz
Max
22
—
Unit
ns
ns
2-23
BG