AK5394AVSP-E2 AKM Semiconductor Inc, AK5394AVSP-E2 Datasheet - Page 15

• Manufacturer Part Number: AK5394AVSP-E2
• Description: IC ADC AUDIO STER 24BIT 28VSOP
• Manufacturer: AKM Semiconductor Inc
• Type: ADCr

Specifications of AK5394AVSP-E2

• Resolution (bits): 24 b
• Sampling Rate (per Second): 1k ~ 216k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 974-1038-1

ASAHI KASEI
1. When the capacitors of 10µF or less are connected between VREF pin and GND:
When RSTN pin goes to “L”, the digital section is powered-down. Upon returning “H”, the offset calibration cycle is
started. The offset calibration cycle should always be initiated after power-up.
During the offset calibration cycle, the digital section of the part measures and stores the values of calibration input of
each channel in registers. The calibration input value is subtracted from all future outputs. The calibration input may be
obtained from either the analog input pins (AIN+/−) or the VCOM pins depending on the state of the ZCAL pin. With
ZCAL “H”, the analog input pin voltages are measured, and with ZCAL “L”, the VCOM pin voltages are measured. The
CAL output is “H” during calibration.
2. When capacitors more than 10µF are connected between VREF pin and GND:
The distortion at low frequency can be improved by connecting large capacitors (C in Figure 5) to VREF pins. (Refer to
Figure 12) However, when the capacitors of VREF pins are larger than 10µF, it is possibility that the offset calibration
does not performed correctly if the offset calibration cycle is started right after power-up. Because the internal VREF can
not settle to the appropriate voltage when the calibration cycle is completed. In this case, the offset calibration cycle
should be started again after the VREF voltage settled. The timing is shown in Figure 6. Table 4 shows the relationship
between the capacitance and the VREF settling time.
MS0137-E-03
Offset Calibration
Table 4. Settling Time and capacitors connected between VREF and GND
C
C
Capacitor
C[µF]
Figure 5. VREF circuit example
+
+
1000
470
220
100
0.22u
1
2
- 15 -
VREFL+
VREFL-
Settling Time
T[s]=5000 x C
2.4
1.1
0.5
AK5394A
5
[AK5394A]
2005/05