AK5388EQP AKM Semiconductor Inc, AK5388EQP Datasheet - Page 17

• Manufacturer Part Number: AK5388EQP
• Description: IC ADC AUDIO STER 24BIT 44LQFP
• Manufacturer: AKM Semiconductor Inc
• Type: ADCr

Specifications of AK5388EQP

• Resolution (bits): 24 b
• Sampling Rate (per Second): 8k ~ 216k
• Data Interface: I²S, Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 3.3V, 5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 974-1035

■
MCLK (128fs/192fs/256fs/384fs/512fs/768fs), BICK (48fs∼) and LRCK (fs) clocks are required in slave mode. The
LRCK clock input must be synchronized with MCLK, however the phase is not critical.
show the relationship of typical sampling frequency and the system clock frequency. MCLK frequency is selected by
CKS1-0 pins as shown in
Since the AK5388 includes a phase detection circuit for LRCK, the AK5388 is reset automatically when the
synchronization is out of phase after changing the clock frequencies.
All external clocks (MCLK, BICK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not
provided, the AK5388 may draw excess current due to its use of internal dynamically refreshed logic. If the external
clocks are not present, place the AK5388 in power-down mode (PDN pin = “L”). In master mode, the master clock
(MCLK) must be provided unless the PDN pin = “L”. In case of using two or more devices, the AK5388 should be reset
by the PDN pin when changing clocks, changing clock modes and switching digital interfaces for a synchronization.
Clock or mode changes should be made during the reset, and a stable clock is needed after the reset.
MS1096-E-01
System Clock
192kHz
192kHz
192kHz
32kHz
48kHz
96kHz
32kHz
48kHz
96kHz
32kHz
48kHz
96kHz
fs
fs
fs
24.576MHz
24.576MHz
24.576MHz
128fs
128fs
128fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Table
4.
36.864MHz
36.864MHz
36.864MHz
Table 2. System Clock Example (Master Mode)
Table 1. System Clock Example (Slave Mode)
Table 3. System Clock Example (Auto Mode)
192fs
192fs
192fs
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
OPERATION OVERVIEW
12.288MHz
24.576MHz
12.288MHz
24.576MHz
24.576MHz
8.192MHz
8.192MHz
256fs
256fs
256fs
N/A
N/A
N/A
N/A
N/A
- 17 -
MCLK
MCLK
MCLK
12.288MHz
18.432MHz
12.288MHz
18.432MHz
36.864MHz
36.864MHz
384fs
384fs
384fs
N/A
N/A
N/A
N/A
N/A
N/A
16.384MHz
24.576MHz
16.384MHz
24.576MHz
16.384MHz
24.576MHz
Table
512fs
512fs
512fs
N/A
N/A
N/A
N/A
N/A
N/A
1,
(N/A: Not available)
(N/A: Not available)
(N/A: Not available)
Table 2
24.576MHz
36.864MHz
24.576MHz
36.864MHz
24.576MHz
36.864MHz
and
768fs
768fs
768fs
N/A
N/A
N/A
N/A
N/A
N/A
[AK5388]
Table 3
2009/08