S-1165B50MC-N7JTFG Seiko Instruments, S-1165B50MC-N7JTFG Datasheet - Page 14

• Manufacturer Part Number: S-1165B50MC-N7JTFG
• Description: IC REG LDO 200MA 5.0V SOT23-5
• Manufacturer: Seiko Instruments

Specifications of S-1165B50MC-N7JTFG

• Regulator Topology: Positive Fixed
• Voltage - Output: 5V
• Voltage - Input: Up to 6.5V
• Voltage - Dropout (typical): 0.14V @ 200mA
• Number Of Regulators: 1
• Current - Output: 200mA (Min)
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 6.5 V
• Output Voltage: 5 V
• Output Type: Fixed
• Dropout Voltage (max): 0.2 V at 200 mA
• Output Current: 200 mA
• Line Regulation: 0.2 % / V
• Load Regulation: 40 mV
• Voltage Regulation Accuracy: 1 %
• Maximum Power Dissipation: 0.3 W
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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HIGH RIPPLE-REJECTION LOW DROPOUT CMOS VOLTAGE REGULATOR
S-1165 Series
Precautions
• This IC performs phase compensation by using an internal phase compensator and the ESR of an
• Wiring patterns for the VIN, VOUT and GND pins should be designed so that the impedance is low.
• Note that the output voltage may increase when a series regulator is used at low load current (1.0 mA or
• The voltage regulator may oscillate when the impedance of the power supply is high and the input
• The application conditions for the input voltage, output voltage, and load current should not exceed the
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
• In determining the output current, attention should be paid to the output current value specified in Table
• SII claims no responsibility for any disputes arising out of or in connection with any infringement by
When mounting an output capacitor between the VOUT and VSS pins (C
the input between VIN and VSS pins (C
short as possible.
less).
output capacitor. Therefore, always place a capacitor of 2.2 μF or more between VOUT and VSS pins.
A tantalum type capacitor is recommended. Moreover, to secure stable operation of the S-1165 Series,
it is necessary to employ a capacitor with an ESR within an optimum range (0.5 to 5 Ω). Using a
capacitor whose ESR is outside the optimum range (approximately 0.5 to 5 Ω), whether larger or
smaller, may cause an unstable output, resulting in oscillation. Perform sufficient evaluation under the
actual usage conditions for selection, including evaluation of temperature characteristics.
capacitor is small or an input capacitor is not connected.
package power dissipation.
electrostatic protection circuit.
4 in the electrical characteristics and footnote *5) of the table.
products including this IC of patents owned by a third party.
Seiko Instruments Inc.
IN
), the distance from the capacitors to these pins should be as
L
) and a capacitor for stabilizing
Rev.4.0
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