MCP1727-3302E/SN Microchip Technology, MCP1727-3302E/SN Datasheet - Page 13

• Manufacturer Part Number: MCP1727-3302E/SN
• Description: IC REG LDO 1.5A 3.3V 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP1727-3302E/SN

• Package / Case: 8-SOIC (3.9mm Width)
• Regulator Topology: Positive Fixed
• Voltage - Output: 3.3V
• Voltage - Input: Up to 6V
• Voltage - Dropout (typical): 0.33V @ 1.5A
• Number Of Regulators: 1
• Current - Output: 1.5A (Min)
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Outputs: 1
• Polarity: Positive
• Input Voltage Max: 6 V
• Output Voltage: 3.3 V
• Output Type: Fixed
• Dropout Voltage (max): 0.55 V at 1.5 A
• Output Current: 1.5 A
• Line Regulation: 0.05 % / V
• Load Regulation: 0.5 %
• Voltage Regulation Accuracy: 2 %
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Primary Input Voltage: 3.85V
• Output Voltage Fixed: 3.3V
• Dropout Voltage Vdo: 330mV
• No. Of Pins: 8
• Voltage Regulator Case Style: SOIC
• Operating Temperature Range: -40°C To
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Limit (min): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.0
The descriptions of the pins are listed in
TABLE 3-1:
3.1
Connect the unregulated or regulated input voltage
source to V
several inches away from the LDO, or the input source
is a battery, it is recommended that an input capacitor
be used. A typical input capacitance value of 1 µF to
10 µF should be sufficient for most applications.
3.2
The SHDN input is used to turn the LDO output voltage
on and off. When the SHDN input is at a logic-high
level, the LDO output voltage is enabled. When the
SHDN input is pulled to a logic-low level, the LDO
output voltage is disabled. When the SHDN input is
pulled low, the PWRGD output also goes low and the
LDO enters a low quiescent current shutdown state
where the typical quiescent current is 0.1 µA.
3.3
Connect the GND pin of the LDO to a quiet circuit
ground. This will help the LDO power supply rejection
ratio and noise performance. The ground pin of the
LDO only conducts the quiescent current of the LDO
(typically 140 µA), so a heavy trace is not required.
3.4
The PWRGD output is an open-drain output used to
indicate when the LDO output voltage is within 92%
(typically) of its nominal regulation value. The PWRGD
output has a typical hysteresis value of 2% for the
adjustable voltage version and for voltage outputs less
than 2.5V. For fixed output voltage versions greater
than 2.5V, the hysteresis is 0.7%. The PWRGD output
is delayed on power-up by 200 µs (typical, no capaci-
tance on C
the C
© 2007 Microchip Technology Inc.
Fixed Output
Exposed Pad
Pin No.
DELAY
—
1
2
3
4
5
6
7
8
PIN DESCRIPTION
Input Voltage Supply (V
Shutdown Control Input (SHDN)
Ground (GND)
Power Good Output (PWRGD)
DELAY
pin.
IN
. If the input voltage source is located
pin). This delay time is controlled by
PIN FUNCTION TABLE
Exposed Pad
Adjustable
Pin No.
Output
—
1
2
3
4
5
6
7
8
IN
Table
PWRGD
C
SHDN
)
Name
V
V
GND
ADJ
DELAY
V
V
EP
OUT
OUT
IN
IN
3-1.
Description
Input Voltage Supply
Input Voltage Supply
Shutdown Control Input (active-low)
Ground
Power Good Output
Power Good Delay Set-Point Input
Output Voltage Sense Input (adjustable version)
Regulated Output Voltage
Regulated Output Voltage
Exposed Pad of the DFN Package
3.5
The C
PWRGD output. By connecting an external capacitor
from the C
PWRGD output can be adjusted from 200 µs (no
capacitance) to 300 ms (0.1 µF capacitor). This allows
for the optimal setting of the system reset time.
3.6
The output voltage adjust pin (ADJ) for the adjustable
output voltage version of the MCP1726 allows the user
to set the output voltage of the LDO by using two
external resistors. The adjust pin voltage is 0.41V
(typical).
3.7
The V
LDO. A minimum output capacitance of 1.0 µF is
required for LDO stability. The MCP1726 is stable with
ceramic, tantalum and aluminum-electrolytic capaci-
tors. See Section 4.3 “Output Capacitor” for output
capacitor selection guidance.
3.8
The 3x3 DFN package has an exposed pad on the bot-
tom of the package. This pad should be soldered to the
Printed Circuit Board (PCB) to aid in the removal of
heat from the package during operation. The exposed
pad is at the ground potential of the LDO.
DELAY
OUT
Power Good Delay Set-Point Input
(C
Output Voltage Sense Input (ADJ)
Regulated Output Voltage (V
Exposed Pad (EP)
DELAY
pin(s) is the regulated output voltage of the
DELAY
input sets the power-up delay time for the
pin to ground, the delay times for the
)
MCP1726
DS21936C-page 13
OUT
)