X40626V14 Intersil, X40626V14 Datasheet - Page 3

• Manufacturer Part Number: X40626V14
• Description: IC SUPERVISOR CPU DUAL 14-TSSOP
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40626V14

• Number Of Voltages Monitored: 2
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 100 ms Minimum
• Voltage - Threshold: 2.93V, 4.38V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X40626 activates a power-
on Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
for t
RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X40626 monitors the V
and asserts RESET if supply voltage falls below a pre-
set minimum V
microprocessor from operating in a power fail or
brownout condition. The RESET signal remains active
until the voltage drops below 1V. It also remains active
until V
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time-out period to
prevent a RESET signal. The state of two nonvolatile
control bits in the Status Register determine the watch-
dog timer period. The microprocessor can change
these watchdog bits, or they may be “locked” by tying
the WP pin HIGH.
Figure 1. Set V
SCL
SDA
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power-up.
WP
PURST
CC
CC
returns and exceeds V
exceeds the device V
(200ms nominal) the circuit releases
0 1 2 3 4 5 6 7
TRIP
TRIP
. The RESET signal prevents the
A0H
Level Sequence (V
3
TRIP
TRIP
0 1 2 3 4 5 6 7
for 200ms.
threshold value
CC
V
P
/V
= 12-15V
00H
2MON
CC
level
= desired V
*for V
for V
X40626
TRIP
0 1 2 3 4 5 6 7
VTRIP2
address is 01H
address is 0DH
EEPROM INADVERTENT WRITE PROTECTION
When RESET goes active as a result of a low voltage
condition or Watchdog Timer Time-Out, any in-
progress communications are terminated. While
RESET is active, no new communications are allowed
and no non-volatile write operation can start. Non-vol-
atile writes in-progress when RESET goes active are
allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
The X40626 is shipped with a standard V
(V
operating and storage conditions. However, in applica-
tions where the standard V
higher precision is needed in the V
X40626 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvol-
atile control signal.
Setting the V
This procedure is used to set the V
lower voltage value. It is necessary to reset the trip
point before setting the new value.
The V
sequence.
To set the new V
bit in the control register, then apply the desired V
threshold voltage to the V
voltage, V
byte of “00” data. The stop bit following a valid write
operation initiates the V
Bring WP LOW to complete the operation.
TRIP
xxH*
CC
TRIP
/V
values, WP = 12-15V when WEL bit set)
CC
2MON
) voltage. This value will not change over normal
and V2MON must be tied together during this
P
, to the WP pin and 2 byte address and 1
THRESHOLD RESET PROCEDURE
TRIP
TRIP
0 1 2 3 4 5 6 7
Voltage
voltage, start by setting the WEL
00H
TRIP
CC
TRIP
pin and the programming
programming sequence.
is not exactly right, or if
TRIP
TRIP
to a higher or
CC
value, the
March 28, 2005
threshold
FN8119.0
TRIP