CAT1640LI-30-G ON Semiconductor, CAT1640LI-30-G Datasheet - Page 9
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CAT1640LI-30-G
Manufacturer Part Number
CAT1640LI-30-G
Description
IC SUPERVSR CPU 64K EEPROM 8PDIP
Manufacturer
ON Semiconductor
Type
Simple Reset/Power-On Resetr
Datasheet
1.CAT1640WI-42-T3.pdf
(18 pages)
Specifications of CAT1640LI-30-G
Number Of Voltages Monitored
1
Output
Open Drain or Open Collector
Reset
Active Low
Reset Timeout
130 ms Minimum
Voltage - Threshold
3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
Monitored Voltage
3 V, 3.3 V, 5 V
Output Type
Active Low, Open Drain
Manual Reset
Resettable
Watchdog
No Watchdog
Battery Backup Switching
No Backup
Supply Voltage (max)
5.5 V
Supply Voltage (min)
3 V
Supply Current (typ)
3000 uA
Maximum Power Dissipation
1000 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Power Fail Detection
No
Undervoltage Threshold
3 V
Overvoltage Threshold
3.15 V
Power-up Reset Delay (typ)
270 ms
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CAT1640LI-30-G
Manufacturer:
ONSemiconductor
Quantity:
2 000
Figure 7. Slave Address Bits
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice.
ACKNOWLEDGE
After a successful data transfer, each receiving device
is required to generate an acknowledge. The
acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
The CAT1640/41 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT1640/41 begins a READ mode it transmits
8 bits of data, releases the SDA line and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT1640/41 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 6. Acknowledge Timing
Figure 5. Start/Stop Timing
Default Configuration
CAT
FROM TRANSMITTER
FROM RECEIVER
SDA
SCL
DATA OUTPUT
DATA OUTPUT
SCL FROM
MASTER
1
START BIT
START
0
1
0
1
A2
9
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information (with
the R/W bit set to zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends two 8-bit
address bytes that are to be written into the address
pointers of the device. After receiving another acknowledge
from the Slave, the Master device transmits the data to be
written into the addressed memory location. The CAT1640/
41 acknowledges once more and the Master generates
the STOP condition. At this time, the device begins an
internal programming cycle to non-volatile memory. While
the cycle is in progress, the device will not respond to any
request from the Master device.
A1
A0
R/W
8
ACKNOWLEDGE
STOP BIT
9
CAT1640, CAT1641
Doc No. MD-3012, Rev. D