ISL88021IU8FCZ-TK Intersil, ISL88021IU8FCZ-TK Datasheet - Page 4

• Manufacturer Part Number: ISL88021IU8FCZ-TK
• Description: IC VOLTAGE MON TRIPLE UV 8-MSOP
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of ISL88021IU8FCZ-TK

• Number Of Voltages Monitored: 3
• Output: Open Drain, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 2.332V, 3.085V, Adj
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL88021IU8FCZ-TKTR

Electrical Specifications
Functional Description
The ISL88021 and ISL88022 devices incorporate such features
as Power-On-Reset control, Supply Voltage Supervision,
Undervoltage or Overvoltage Monitoring, and Manual Reset
Assertion.
The ISL88021 and ISL88022 devices provide common preset
threshold voltages on both V
optional resistor divider network on V3MON to provide custom
voltage monitoring of voltages greater than 0.6V. An optional
capacitor can be connected between the C
increase the nominal 200ms t
operational functionality with a timing diagram.
Voltage Monitoring
During normal operation, the ISL88021 and ISL88022 monitor
the voltage levels on V
ISL88021 asserts reset if any one of these voltages fall below
their respective voltage trip points and in the case of ISL88022
above the voltage trip point on the V3MON input. The reset
signal effectively prevents the microprocessor from operating
during a power failure, brownout or over voltage condition. This
signal remains active until all monitored voltages meet all
voltage threshold requirements for the reset time delay period
t
for design flexibility. Figure 1 illustrates the VDD, V2MON and
V3MON input threshold voltages for the various available
options.
POR
MANUAL RESET
SYMBOL
V
V
R
t
. Note that both RESET and RESET signals are provided
MRH
MRL
MR
PU
FIGURE 1. VDD, V2MON, V3MON VTH vs TEMP
5.000
4.500
4.000
3.500
3.000
2.500
2.000
1.500
1.000
0.500
0.000
MR Input Voltage Low
MR Input Voltage High
MR Minimum Pulse Width
Internal Pull-Up Resistor
-40
DD
, V2MON and V3MON. The
TEMPERATURE (°C)
DD
PARAMETER
POR
4
Vth = 4.64V
and V2MON and for an
Vth = 1.69V
Vth = 3.09V
Vth = 2.32V
Vth = 2.92V
Vth = 0.60V
Over the recommended operating conditions unless otherwise specified. (Continued)
delay. Figure 7 illustrates
25
POR
pin and GND to
85
ISL88021, ISL88022
TEST CONDITIONS
Power-On-Reset (POR)
Applying power to the ISL88021 and ISL88022 devices
activates a POR circuit which holds the RESET pin low once
V
• It prevents the system microprocessor from starting to
• It prevents the processor from operating prior to
• It ensures that the monitored device is held out of operation
• It allows time for an FPGA to download its configuration prior
When all of the monitored voltages meet their respective
input voltage requirements for the specified reset timeout
delay t
output low and releases the RST output to allow the system
to begin operation.
Adjusting t
On the ISL88021 and ISL88022, users can adjust the
Power-On-Reset timeout delay (t
nominal t
on the C
graph normalized to 175ms for an open C
maximum recommended capacitance that should be placed
on the C
PCB layout and capacitor placement in order to eliminate
stray capacitance as much as possible, which contributes to
t
POR
DD
operate with insufficient voltage.
stabilization of the oscillator.
until internal registers are properly loaded.
to initialization of the circuit.
> 1V. This signal provides several benefits:
error.
POR
FIGURE 2. NORMALIZED t
10
POR
POR
8
6
4
2
0
POR
, the POR circuit simultaneously pulls the RST
1
POR
. Figure 2 illustrates the effect of capacitance
pin is 50pF. NOTE: Care should be taken in
pin to ground, showing changing t
5
9 13 17 21 25 29 33 37 41 45
V
DD
MIN
550
-0.6
C
POR
POR
POR
TYP
20
(pF)
) to many times the
vs C
POR
POR
MAX
0.8
GRAPH
September 18, 2006
pin. The
POR
UNITS
with a
FN8226.1
kΩ
ns
V
V