S-80945CNMC-G9FT2G Seiko Instruments, S-80945CNMC-G9FT2G Datasheet - Page 12

• Manufacturer Part Number: S-80945CNMC-G9FT2G
• Description: IC VOLT DETECTOR 4.5V SOT23-5
• Manufacturer: Seiko Instruments
• Type: Simple Reset/Power-On Resetr

Specifications of S-80945CNMC-G9FT2G

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 20 ms Minimum
• Voltage - Threshold: 4.5V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Output Type: Open Collector / Drain
• Undervoltage Threshold: 4.5 V
• Power-up Reset Delay (typ): Adj
• Supply Voltage (min): 0.7 V
• Supply Voltage (max): 10 V
• Supply Current (typ): 1.3 uA
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Description/function: Open-drain and CMOS output,
• Detection Range: 4.5 V +/- 2 %
• Internal Hysteresis: Yes
• Manual Reset: No
• Operating Supply Voltage: 0.7 V to 10 V
• Watchdog: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12
ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
S-809xxC Series
1. Basic Operation: CMOS Output (Active Low)
Operation
1-1. When the power supply voltage (V
1-2. When the V
1-3. When the V
1-4. The V
1-5. When V
OFF and the Pch transistor is ON to provide V
Figure 14 is OFF, the comparator input voltage is
the detection voltage −V
transistor becomes ON, the Pch transistor becomes OFF, and the V
this time the Nch transistor N1 in Figure 14 becomes ON, the comparator input voltage is changed to
the V
appears even when the V
+V
transistor becomes ON, and V
circuit.
R
R
B
A
DET
•
+
V
DD
.
R
SS
DD
B
DD
when the output is pulled up to the V
level appears when the V
.
rises above +V
DD
DD
*1. Parasitic diode
goes below +V
falls below the minimum operating voltage, the output becomes undefined, or goes to
*1
V
V
DD
V
REF
DET
SS
DET
DD
. When the V
surpasses −V
R
R
R
(point B in Figure 15), the Nch transistor becomes OFF, and the Pch
DET
DD
B
C
A
+
−
, the output provides the V
appears at the output after the delay time (t
DD
Seiko Instruments Inc.
DD
Figure 14 Operation 1
) is higher than the release voltage (+V
rises above the minimum operating voltage. The V
N1
DD
DET
circuit
Delay
falls below −V
DD
, as long as it does not exceed the release voltage
DD
.
(high) at the output. Since the Nch transistor N1 in
CD
C
R (
D
R
*1
B
Pch
A
Nch
+
+
R
R
DET
C
B
DD
)
+
•
level, as long as the V
(point A in Figure 15), the Nch
R
V
C
DD
*1
*1
.
SS
level appears at the output. At
OUT
DET
D
) counted by the delay
), the Nch transistor is
DD
remains above
SS
Rev.4.0
level still
_00