S-80126BNMC-JGLT2G Seiko Instruments, S-80126BNMC-JGLT2G Datasheet - Page 14

• Manufacturer Part Number: S-80126BNMC-JGLT2G
• Description: IC VOLT DETECTOR 100MS SOT23-5
• Manufacturer: Seiko Instruments
• Type: Simple Reset/Power-On Resetr

Specifications of S-80126BNMC-JGLT2G

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 65 ms Minimum
• Voltage - Threshold: 2.6V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-5, SC-74A, SOT-25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14
ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (INTERNAL DELAY TIME SETTING)
S-801 Series
Operation
1. Basic Operation: CMOS Output (Active Low)
1-1. When the power supply voltage (V
1-2. When the V
1-3. When the V
1-4. The V
1-5. When V
transistor is OFF and the Pch transistor is ON to provide V
Nch transistor N1 in Figure 10 is OFF, the comparator input voltage is
above the detection voltage (–V
the Nch transistor becomes ON, the Pch transistor becomes OFF, and the V
at the output. At this time the Nch transistor N1 in Figure 10 becomes ON, the comparator
input voltage is changed to
goes to V
appears even when V
voltage +V
Pch transistor becomes ON to provide V
t
D
due to the delay circuit.
SS
DD
level appears when V
*1. Paracitic diode
rises above +V
DD
DD
DD
DET
when the output is pulled up to V
goes below +V
falls below the minimum operating voltage, the output becomes undefined, or
V
V
.
V
DD
REF
SS
R
R
R
A
DD
C
B
+
−
DET
surpasses the –V
Seiko Instruments Inc.
R
(point B in Figure 11), the Nch transistor becomes OFF and the
DET
N1
R
DD
B
A
, the output provides the V
•
rises above the minimum operating voltage. The V
Figure 10 Operation 1
DET
+
V
DD
R
Delay circuit
DD
). When the V
B
) is higher than the release voltage (+V
.
DD
DET
at the output. The V
DS
DD
, as long as it does not exceed the release
.
DD
Pch
Nch
falls below –V
DD
DD
level, as long as V
(high) at the output. Since the
DD
*1
*1
at the OUT pin is delayed for
DET
(point A in Figure 11),
OUT
R (
R
B
A
DET
+
+
SS
R
), the Nch
R
C
DD
B
level appears
Rev.4.0
)
+
•
remains
SS
R
V
C
DD
level still
.
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