LTC690CN8 Linear Technology, LTC690CN8 Datasheet - Page 12

• Manufacturer Part Number: LTC690CN8
• Description: IC MPU SUPERVISORY CIRCUIT 8-DIP
• Manufacturer: Linear Technology
• Type: Simple Reset/Power-On Resetr

Specifications of LTC690CN8

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LTC690/LTC691
LTC694/LTC695
APPLICATIONS INFORMATION
12
V
+
V
5V
IN
5V
0.1μF
IN
0.1μF
≥ 6.5V
10μF
R1
51k
R2
10k
≥ 7.5V
Figure 6. A Typical Nonvolatile CMOS RAM Application
3V
Figure 7. Write Protect for RAM with LTC690 or LTC694
10μF
3V
+
Figure 8. Monitoring Unregulated DC Supply
with the LTC690’s Power-Fail Comparator
V
LT1086-5
Figure 9. Monitoring Regulated DC Supply
with the LTC690’s Power-Fail Comparator
IN
ADJ
V
V
V
V
V
BATT
CC
V
CC
BATT
LT1086-5
IN
GND
OUT
LTC690
LTC694
LTC691
LTC695
ADJ
GND
V
RESET
CE OUT
OUT
RESET
+
RESET
V
CE IN
OUT
V
OUT
10μF
+
+
+
100μF
300k
R1
27k
R2
8.2k
R5
3.3k
20ns PROPAGATION DELAY
R3
TO μP
10μF
FROM DECODER
10μF
2.7M
5V
R3
10k
R4
R4
10k
0.1μF
5V
0.1μF
0.1μF
0.1μF
CS
TO μP
PFI
PFO
LTC690/LTC691
LTC694/LTC695
V
TO μP
CC
PFO
PFI
V
LTC690/LTC691
LTC694/LTC695
CC
CS1
CS2
V
CS
V
GND
CC
CC
GND
62512
RAM
GND
GND
62128
RAM
690 F06
690 F07
690 F08
1690 F09
Power-Fail Warning
The LTC690 family generates a Power Failure Output
(PFO) for early warning of failure in the microprocessor’s
power supply. This is accomplished by comparing the
Power Failure Input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The voltage
divider ratio can be chosen such that the voltage at the PFI
pin falls below 1.3V several milliseconds before the 5V
supply falls below the maximum reset voltage threshold
4.75V. PFO is normally used to interrupt the microprocessor
to execute shutdown procedure between PFO and RESET
or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resistor
between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the summing
junction at the PFI pin.
When PFO output is high, the series combination of R3
and R4 source current into the PFI summing junction.
Example 1: The circuit in Figure 8 demonstrates the use
of the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input V
shutdown procedure is 8ms. Also the noise of V
With these assumptions in mind, we can reasonably set
V
reset voltage threshold and the dropout voltageof LT1086-5
(4.75V + 1.5V) and V
L
= 7.5V which 1.25V greater than the sum of maximum
V = 1.3V 1+
V
Assuming R4
H
L
=
1.3V 1
⎛
⎜
⎝
⎛
⎜
⎝
IN
is 100mV/ms and the total time to execute a
+
R2
R1
R2
R1
<<
HYSTERESIS
+
–
R3,V
R3
1.3V(R3 R4)
R1
(5V – 1.3V)R1
⎞
⎟
⎠
HYSTERESIS
= 850mV.
+
⎞
⎟
⎠
=
5V
IN
R3
R1
is 200mV.
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