LTC2900-1IDD#TRPBF Linear Technology, LTC2900-1IDD#TRPBF Datasheet - Page 11

• Manufacturer Part Number: LTC2900-1IDD#TRPBF
• Description: IC MON SUPP QUAD OPEN DRN 10DFN
• Manufacturer: Linear Technology
• Type: Multi-Voltage Supervisorr

Specifications of LTC2900-1IDD#TRPBF

• Number Of Voltages Monitored: 4
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 5 ms Minimum
• Voltage - Threshold: 16 Selectable Threshold Combinations
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-WFDFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
Although all four supply monitor comparators have built-
in glitch immunity, bypass capacitors on V1 and V2 are
recommended because the greater of V1 or V2 is also the
V
inputs are allowed.
Power-Down
On power-down, once any of the V
their threshold, RST is held at a logic low. A logic low of
0.4V is guaranteed until both V1 and V2 drop below 1V. If
the bandgap reference becomes invalid (V
part will reprogram once V
Monitor Output Rise and Fall Time Estimation
The RST output has strong pull-down capability. If the
external load capacitance (C
time (10% to 90%) is estimated using:
where R
transistor. The typical performance curve (V
demonstrates that the pull-down current is somewhat
linear versus output voltage. Using the 25 C curve, R
estimated to be approximately 40 . Assuming a 150pF
load capacitance, the fall time is about 13.2ns.
Although the RST output of the LTC2900-1 is considered
to be “open-drain,” it does have weak pull-up capability
(see RST Pull-Up Current vs V2 curve). Output rise time
(10% to 90%) is estimated using:
where R
The on-resistance as a function of the V2 voltage at room
temperature is estimated using:
CC
t
t
FALL
RISE
for the device. Filter capacitors on the V3 and V4
PD
PU
2.2 • R
2.2 • R
is the on-resistance of the internal pull-down
is the on-resistance of the pull-up transistor.
PD
PU
U
• C
• C
LOAD
LOAD
U
CC
LOAD
rises above 2.4V max.
) is known, output fall
W
X
inputs drop below
CC
< 2V typ), the
OL
U
vs I
SINK
PD
is
)
with V2 = 3.3V, R
capacitance, the rise time is 86 s. If the output needs to
pull up faster and/or to a higher voltage, a smaller
external pull-up resistor may be used. Using a 10k pull-
up resistor, the rise time is reduced to 3.3 s for a 150pF
load capacitance.
The LTC2900-2 has an active pull-up to V2 on the RST
output. The typical performance curve (RST Pull-Up Cur-
rent vs V2 curve) demonstrates that the pull-up current is
somewhat linear versus the V2 voltage and R
mated to be approximately 625 . A 150pF load capaci-
tance makes the rise time about 206ns.
Selecting the Reset Timing Capacitor
The reset time-out period is adjustable in order to accom-
modate a variety of microprocessor applications. The
reset time-out period, t
capacitor, C
of this capacitor is determined by:
with C
millisecond of delay can also be expressed as C
217 (pF/ms).
Leaving the CRT pin unconnected will generate a mini-
mum reset time-out of approximately 50 s. Maximum
reset time-out is limited by the largest available low
leakage capacitor. The accuracy of the time-out period will
be affected by capacitor leakage (the nominal charging
current is 2 A) and capacitor tolerance. A low leakage
ceramic capacitor is recommended.
C
R
RT
PU
RT
= t
in Farads and t
RST
6 10
V
RT
•
2 1
• 217 • 10
–
, between the CRT pin and ground. The value
5
PU
is about 260k. Using 150pF for load
RST
RST
–9
, is adjusted by connecting a
in seconds. The C
LTC2900
RT
PU
value per
RT
11
is esti-
/ms =
2900f