DS1706SESA+ Maxim Integrated Products, DS1706SESA+ Datasheet - Page 3

• Manufacturer Part Number: DS1706SESA+
• Description: IC MICROMONITOR 3.3V 10% 8-SOIC
• Manufacturer: Maxim Integrated Products
• Series: MicroMonitor™r
• Type: Simple Reset/Power-On Resetr

Specifications of DS1706SESA+

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 130 ms Minimum
• Voltage - Threshold: 2.93V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Monitored Voltage: 3.3 V or 5 V
• Undervoltage Threshold: 2.85 V
• Overvoltage Threshold: 3 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 285 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.2 V
• Supply Current (typ): 60 uA
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Chip Enable Signals: No
• Minimum Operating Temperature: - 40 C
• Output Type: Active Low or Push-Pull
• Power Fail Detection: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Watchdog Timer
The watchdog timer function forces
second time-out period. Time-out of the watchdog starts when
to-low transition occurs on the
time out again. If the watchdog timer is allowed to time out, the
minimum of 130 ms. The
used are the microprocessors address signals, data signals, or control signals. When the microprocessor
functions normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to
time-out. To guarantee that the watchdog timer does not time out, a high-to-low transition must occur at
or less than the minimum watchdog time-out of 1 second. A typical circuit example is shown in Figure 6.
MICROMONITOR BLOCK DIAGRAM Figure 1
PUSH-BUTTON RESET Figure 2
40k
180k
ST
input can be derived from many microprocessor outputs. The typical signals
ST
input pin prior to time-out, the watchdog timer is reset and begins to
WDS
signals active when the
3 of 12
RST
WDS
(or RST) becomes inactive. If a high-
ST
signal is driven active (low) for a
input is not clocked within the 1