ADM706SARZ Analog Devices Inc, ADM706SARZ Datasheet - Page 10

• Manufacturer Part Number: ADM706SARZ
• Description: IC SUPERVISOR MPU 2.93 WD 8SOIC
• Manufacturer: Analog Devices Inc
• Type: Simple Reset/Power-On Resetr

Specifications of ADM706SARZ

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 160 ms Minimum
• Voltage - Threshold: 2.93V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Threshold Voltage: 4.4V
• No. Of Supervisors / Monitors: 1
• Supply Voltage Range: 1V To 5.5V
• Reset Type: Active-Low
• Supply Current: 190µA
• Delay Time: 200ms
• Digital Ic Case Style: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T
CIRCUIT INFORMATION
POWER-FAIL RESET
The reset output provides a reset (RESET or RESET ) output
signal to the microprocessor whenever the V
the reset threshold. The actual reset threshold voltage is dependent
on whether a P, R, S, or T suffix device is used. An internal timer
holds the reset output active for 200 ms after the voltage on V
rises above the threshold. This is intended as a power-on reset
signal for the microprocessor. It allows time for both the power
supply and the microprocessor to stabilize after power-up. If a
power supply brownout or interruption occurs, the reset line is
similarly activated and remains active for 200 ms after the supply
recovers. If another interruption occurs during an active reset
period, the reset timeout period continues for an additional 200 ms.
The reset output is guaranteed to remain valid with V
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.
The ADM706P provides an active high RESET signal; the
ADM706R/ADM706S/ADM706T provide an active low RESET
signal; and the ADM708R/ADM706S/ADM706T provide both
RESET and RESET .
POWER-FAIL
POWER-FAIL
WATCHDOG
INPUT (WDI)
INPUT (PFI)
INPUT (PFI)
V
V
MR
MR
CC
CC
* VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)
* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)
V
1.25V
Figure 13. ADM706 Functional Block Diagram
Figure 14. ADM708 Functional Block Diagram
1.25V
V
REF
REF
TRANSITION
WATCHDOG
V
DETECTOR
V
CC
*
*
CC
70μA
70μA
ADM706P/ADM706R/
ADM706S/ADM706T
ADM708R/ADM708S/
GENERATOR
GENERATOR
WATCHDOG
RESET AND
WATCHDOG
TIMEBASE
RESET
RESET
TIMER
ADM708T
CC
input is below
WATCHDOG
OUTPUT (WDO)
POWER-FAIL
OUTPUT (PFO)
RESET,
(P = RESET)
RESET
RESET
POWER-FAIL
OUTPUT (PFO)
CC
as low
Rev. C | Page 10 of 16
CC
RESET
MANUAL RESET
The MR input allows other reset sources, such as a manual reset
switch, to generate a processor reset. The input is effectively
debounced by the timeout period (200 ms typical). The MR
input is TTL-/CMOS-compatible; it can also be driven by any
logic reset output. If unused, the MR input can be tied high or
left floating.
WATCHDOG TIMER (ADM706x)
The watchdog timer circuit is used to monitor the activity of the
microprocessor to check that it is not stalled in an indefinite loop.
An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the timeout
period (1.6 seconds), the watchdog output ( WDO ) is driven low.
The WDO output is connected to a nonmaskable interrupt (NMI)
on the processor. Therefore, if the watchdog timer times out, an
interrupt is generated. The interrupt service routine is used to
rectify the problem.
The watchdog timer is cleared either by a high-to-low or by a
low-to-high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/ RESET going
active. Therefore, the watchdog timeout period begins after
reset goes inactive.
When V
whether or not the watchdog timer has timed out. Normally,
this generates an interrupt, but it is overridden by RESET/ RESET
going active.
RESET
WDO
WDO
WDI
V
t
MR
CC
WP
CC
falls below the reset threshold, WDO is forced low
V
NOTES
RESET = COMPLEMENT OF RESET
RT
Figure 15. RESET , MR , and WDO Timing
Figure 16. Watchdog Timing
t
WD
V
RT
RESET EXTERNALLY
TRIGGERED BY MR
t
RS
t
WD
MR EXTERNALLY
DRIVEN LOW
t
t
RS
RS
t
WD