CLC5665IN National Semiconductor, CLC5665IN Datasheet - Page 9

• Manufacturer Part Number: CLC5665IN
• Description: IC AMP LOW DISTORTION 8-DIP
• Manufacturer: National Semiconductor

Specifications of CLC5665IN

• Amplifier Type: Current Feedback
• Number Of Circuits: 1
• Slew Rate: 1800 V/µs
• -3db Bandwidth: 90MHz
• Current - Input Bias: 3µA
• Voltage - Input Offset: 15000µV
• Current - Supply: 11mA
• Current - Output / Channel: 85mA
• Voltage - Supply, Single/dual (±): 10 V ~ 30 V, ±5 V ~ 15 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Gain Bandwidth Product: -
• Other names: *CLC5665IN

Application Division
2nd and 3rd Harmonic Distortion
To meet low distortion requirements, recognize the effect of
the feedback resistor. Increasing the feedback resistor will
decrease the loop gain and increase distortion. Decreasing
the load impedance increases 3rd harmonic distortion more
than 2nd.
Differential Gain and Differential Phase
The CLC5665 has low DG and DP errors for video applica-
tions. Add an external pulldown resistor to the CLC5665’s
output to improve DG and DP as seen in Figure 4 . A 604
R
Printed Circuit Layout
To get the best amplifier performance careful placement of
the amplifier, components and printed circuit traces must be
observed. Place the 0.1µF ceramic decoupling capacitors
less than 0.1 (3mm) from the power supply pins. Place the
6.8µF tantalum capacitors less than 0.75 (20mm) from the
power supply pins. Shorten traces between the inverting pin
and components to less than 0.25 (6mm). Clear ground
plane 0.1 (3mm) away from pads and traces that connect to
the inverting, non-inverting and output pins. Do not place
ground or power plane beneath the op amp package. Na-
tional provides literature and evaluation boards 730013 DIP
or 730027 SOIC illustrating the recommended op amp lay-
out.
P
V
FIGURE 3. Equivalent Disabled Output Impedance
will improve DG and DP to 0.01% and 0.02˚.
FIGURE 4. Improved DG and DP Video Amplifier
in
100k
100
10k
1M
10
1k
1
R
1
in
R
g
+
-
CLC5665
Frequency (MHz)
R
f
DG and DP
Add R to
improve
10
(Continued)
p
-V
cc
R
p
R
s
DS015015-24
DS015015-23
V
out
100
9
Applications Circuits
Level Shifting
The circuit shown in Figure 5 implements level shifting by AC
coupling the input signal and summing a DC voltage. The
resistor R
frequency. The amplifier closed-loop bandwidth is fixed by
the selection of R
5 are different. The AC gain is set by the ratio of R
And the DC gain is set by the parallel combination of R
R
Multiplexing
Multiple signal switching is easily handled with the disable
function of the CLC5665. Board trace capacitance at the
output pin will affect the frequency response and switching
transients. To lessen the effects of output capacitance place
a resistor (R
as shown in Figure 6 . To match the mux output impedance to
a transmission line, add a resistor (R
output.
Differential Line Driver With Load Impedance Conver-
sion
The circuit shown in Figure 7 , operates as a differential line
driver. The transformer converts the load impedance to a
value that best matches the CLC5665’s output capabilities.
The single-ended input signal is converted to a differential
signal by the CLC5665. The line’s characteristic impedance
V
FIGURE 6. Output Connection for Multiplexing Circuits
V
2
out
.
in1
V
R
in
in
AC
V
V
in
in
DC
in
V
ac
in2
o
R
and the capacitor C set the high pass break
FIGURE 5. Level Shifting Circuit
C
) within the feedback loop to isolate the outputs
in
1
R
R
g
f
2
. The DC and AC gains for circuit of Figure
R
R
in
g
R
R
R
g
f
g
R
CLC5665
+
+
CLC5665
-
-
2
-
+
CLC5665
DIS1
R
DIS2
R
f
f
V
R
in
f
DC
R
R
s
o
o
) in series with the
R
R
2
f
R
www.national.com
DS015015-26
s
DS015015-27
f
and R
V
out
g
V
R
and
out
L
g
.