CLC5523IM National Semiconductor, CLC5523IM Datasheet - Page 14

• Manufacturer Part Number: CLC5523IM
• Description: IC AMP VARIABLE GAIN 8-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC5523IM

• Amplifier Type: Variable Gain
• Number Of Circuits: 1
• Slew Rate: 1800 V/µs
• -3db Bandwidth: 250MHz
• Current - Input Bias: 3µA
• Current - Supply: 13.5mA
• Current - Output / Channel: 80mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Voltage - Supply, Single/dual (±): -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Other names: *CLC5523IM

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Application Division
Digital Gain Control
Digitally variable gain control can be easily realized by driv-
ing the CLC5523’s gain control input with a digital-to-analog
Fast Response AGC Loop
The AGC circuit shown in Figure 11 will correct a 6dB input
amplitude step in 100ns. The circuit includes a two op-amp
precision rectifier amplitude detector (U1 and U2), and an
integrator (U3) to provide high loop gain at low frequencies.
The output amplitude is set by R9.
Some notes on building fast AGC loops:
Precision rectifiers work best with large output signals. Ac-
curacy is improved by blocking DC offsets, as shown in
Figure 11 .
Signal frequencies must not reach the gain control port of the
CLC5523, or the output signal will be distorted (modulated
by itself). A fast settling AGC needs additional filtering be-
yond the integrator stage to block signal frequencies. This is
provided in Figure 11 by a simple R-C filter (R10 and C3);
better distortion performance can be achieved with a more
complex filter. These filters should be scaled with the input
signal frequency. Loops with slower response time (longer
integration time constants) may not need the R10 - C3 filter.
Checking the loop stability can be done by monitoring the V
voltage while applying a step change in input signal ampli-
(Continued)
FIGURE 10. Digital Gain Control
g
14
converter (DAC). Figure 10 illustrates such an application.
This circuit employs National Semiconductor’s eight-bit
DAC0830, the LM351 JFET input op amp, and the CLC5523
VGA. With V
scale resolution. The maximum gain of this circuit is 20dB.
tude. Changing the input signal amplitude can be easily
done with either an arbitrary waveform generator or a fast
multiplexer such as the CLC532.
Automatic Gain Control (AGC) # 2
Figure 12 on the following page, illustrates an automatic gain
control circuit that employs two CLC5523’s. In this circuit, U1
receives the input signal and produces an output signal of
constant amplitude. U2 is configured to provide negative
feedback. U2 generates a rectified gain control signal that
works against an adjustable bias level which may be set by
the potentiometer and R
tive feedback. The resultant gain control signal is applied to
the U1 gain control input V
U1 output to be set at an arbitrary level less than the maxi-
mum output specification of the amplifier. Rectification is
accomplished in U2 by driving both the amplifier input and
the gain control input with the U1 output signal. The voltage
divider that is formed by R1, R2 and the V
resistance, sets the rectifier gain.
ref
set to 2V, the circuit provides up to 0.05% full
DS012798-42
b
. C
g
. The bias adjustment allows the
i
integrates the bias and nega-
g
input (pin 1)