LM6218WM National Semiconductor, LM6218WM Datasheet - Page 7

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LM6218WM

Manufacturer Part Number
LM6218WM
Description
IC OP AMP DUAL FST SETLNG 14SOIC
Manufacturer
National Semiconductor
Series
VIP™r
Datasheet

Specifications of LM6218WM

Amplifier Type
General Purpose
Number Of Circuits
2
Slew Rate
140 V/µs
Gain Bandwidth Product
17MHz
Current - Input Bias
200nA
Voltage - Input Offset
200µV
Current - Supply
5.5mA
Current - Output / Channel
20mA
Voltage - Supply, Single/dual (±)
±5 V ~ 20 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Output Type
-
-3db Bandwidth
-
Other names
*LM6218WM

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Application Information
50 . Connect a small capacitor directly from the amplifier
output to the inverting input. The feedback loop is closed
from the isolated output with a series resistor to the inverting
input.
For C
Settling time to 0.01%, 10V Step
For C
For C
L
= 1000 pF, Small signal BW = 5 MHz
L
L
= 1000 pF, settling time
= 300 pF, settling time
20 V
p-p
BW = 500 kHz
Voltage Follower
Inverter
500 ns
1500 ns
DS010254-10
(Continued)
DS010254-11
7
Examples of unity gain connections for a voltage follower,
Inverter, and integrator driving capacitive loads up to
1000 pF are shown here. Different R1–C1 time constants
and capacitive loads will have an effect on settling times.
Input Bias Current Compensation
Input bias current of the first op amp can be reduced or
balanced out by the second op amp. Both amplifiers are laid
out in mirror image fashion and in close proximity to each
other, thus both input bias currents will be nearly identical
and will track with temperature. With both op amp inputs at
the same potential, a second op amp can be used to convert
bias current to voltage, and then back to current feeding the
first op amp using large value resistors to reduce the bias
current to the level of the offset current.
Examples are shown here for an inverting application, (a)
where the inputs are at ground potential, and a second
circuit (b) for compensating bias currents for both inputs.
Integrator
DS010254-12
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