CLC520AJE National Semiconductor, CLC520AJE Datasheet - Page 9

• Manufacturer Part Number: CLC520AJE
• Description: IC AMP CTRL GAIN/AGC 14-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC520AJE

• Amplifier Type: Current Feedback
• Number Of Circuits: 1
• Slew Rate: 2000 V/µs
• -3db Bandwidth: 160MHz
• Current - Input Bias: 12µA
• Current - Supply: 28mA
• Current - Output / Channel: 60mA
• Voltage - Supply, Single/dual (±): 10 V ~ 14 V, ±5 V ~ 7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Output Type: -
• Gain Bandwidth Product: -
• Voltage - Input Offset: -
• Other names: *CLC520AJE

Application Information
Simplified Circuit Description
A simplified schematic for the CLC520 is given in Figure 1 .
+V
ers inducing a signal current in R
(+V
trols a current source which supplies two well matched tran-
sistors, Q1 and Q2.
The current flowing through Q2 is converted to the final
output voltage using R
ing the fraction of the signal current I which flows through Q2
the gain is changed. This is done by changing the voltage
applied differentially to the bases of Q1 and Q2. For ex-
ample, with V
current of flowing through Q2 into R
minimum gain. Conversely, with V
the signal current I flows through Q2 to R
mum gain. With V
set to approximately the same voltage, causing their collec-
tor currents to equally divide the signal current I, and estab-
lish the gain at one half the maximum gain.
Typical application circuit
Figure 2 illustrates a voltage-controlled gain block offering
broadband performance in a 50
input signal is applied to pin 3 of the CLC520 and terminating
resistor R2. Gain control signals are applied to pin 2. The net
gain control port input impedance is 50 , set by the parallel
combination of R1 and the 750 input impedance of pin 2 of
the CLC520. R
sets the maximum voltage gain to 10V/V. Output impedance
is set by R
tions, the gain is approximately 14dB.
IN
IN
and −V
)−(−V
FIGURE 1. CLC520 Simplified Schematic
IN
o
IN
), the differential input voltage. This current con-
to 50
g
are buffered with closed-loop voltage follow-
= 0, Q1 is on and Q2 is off. With zero signal
f
is set to the standard value, 1k , and R
g
set to 1.1V, the bases of Q1 and Q2 are
so with 50
f
and output amplifier, U1. By chang-
g
source and load termina-
system environment. The
= 2V, Q1 is off and all of
f
, the CLC520 is set to
g
f
producing maxi-
proportional to
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g
9
Capacitors C1-C6 provide broadband power supply bypass-
ing. C2 and C5 should be tantalum capacitors. All other
capacitors should be high quality ceramic capacitors (CK-05
or equivalent).
Adjusting offset
Offset can be broken into two parts; an input-referred term
and an output-referred term. The input-referred offset shows
up as a variation in output voltage as V
be trimmed using the circuit in Figure 3 by placing a low
frequency square wave (V
the input referred V
riding a DC value. Adjust R
to zero. After adjusting the input-referred offset, adjust R2
(with V
applications V
adjustment to pin 3. This offset trim does not improve output
offset temperature coefficient.
Selecting component values
Most applications of the CLC520 adjust the gain to maximize
the V
FIGURE 3. CLC520 Offset Adjustment Circuitry
FIGURE 2. CLC520 Typical Application Circuit
OUT
IN
= 0, V
signal. When referred back to the input, this means
(other external elements not shown)
IN
g
= 0) until V
may be applied to pin 6 and the offset
os
term shows up as a small square wave
IN
1
to null the V
OUT
= 0 to 2V, into V
is zero. Finally, for inverting
g
is changed. This can
os
square wave term
g
with V
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01275608
IN
= 0V,
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