AD8129AR-REEL Analog Devices Inc, AD8129AR-REEL Datasheet - Page 35

• Manufacturer Part Number: AD8129AR-REEL
• Description: IC AMP DIFF LN LDIST 40MA 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8129AR-REEL

• Rohs Status: RoHS non-compliant
• Amplifier Type: Differential
• Number Of Circuits: 1
• Slew Rate: 1070 V/µs
• -3db Bandwidth: 200MHz
• Current - Input Bias: 500nA
• Voltage - Input Offset: 200µV
• Current - Supply: 13mA
• Current - Output / Channel: 40mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 25.2 V, ±2.25 V ~ 12.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Output Type: -
• Gain Bandwidth Product: -

One way to accomplish this is to drive both REF and R
the desired offset signal (see Figure 139). Superposition can be
used to solve this circuit. First, break the connection between
V
is 1 + R
is −R
impedance source, this works fine. However, if the delivered
offset voltage is derived from a high impedance source, such as
a voltage divider, its impedance affects the gain equation. This
makes the circuit more complicated because it creates an
interaction between the gain and offset voltage.
A way around this is to apply the offset voltage to a voltage
divider whose attenuation factor matches the gain of the
amplifier and then apply this voltage to the high impedance
REF input. This circuit first divides the desired offset voltage
by the gain, and the amplifier multiplies it back up to unity (see
Figure 140).
V
RESISTORLESS GAIN OF 2
The voltage applied to the REF input (Pin 4) can also be a high
bandwidth signal. If a unity-gain AD8130 has both +IN and
REF driven with the same signal, there is unity gain from V
and unity gain from V
requires no resistors (see Figure 141).
Figure 139. In this Circuit, V
V
Figure 140. Adding an Attenuator at the Offset Input Causes It to Appear at
OFFSET
OFFSET
OFFSET
F
/R
and R
F
AD8129/
AD8130
/R
G
Circuit Works Well if the V
AD8129/
V
. The sum of these is 1. If V
AD8130
R
V
R
IN
F
G
IN
G
. With Pin 4 grounded, the gain though R
R
G
R
G
G
. With R
1
8
4
5
1
8
4
5
+
+
+
+
the Output with Unity Gain.
R
R
F
REF
F
G
OFFSET
grounded, the gain from Pin 4 to V
PD
. Thus, the circuit has a gain of 2 and
PD
3
3
–V
–V
–V
Appears at the Output with Unity Gain. This
–V
2
2
S
S
+V
+V
+V
OFFSET
+V
7
7
S
S
6
0.1 μ F
6
0.1 μ F
Source Impedance Is Low.
0.1 μ F
REF
0.1 μ F
V
V
is delivered from a low
V
V
OUT
IN
10 μ F
10 μ F
OUT
IN
× (1 + R
× (1 + R
=
10 μ F
=
10 μ F
F
/R
F
/R
G
G
) + V
) + V
G
G
to V
OFFSET
OFFSET
with
OUT
OUT
IN
Rev. C | Page 35 of 40
SUMMER
A general summing circuit can be made by the previous
technique. A unity-gain configured AD8130 has one signal
applied to +IN, while the other signal is applied to REF. The
output is the sum of the two input signals (see Figure 142).
This circuit offers several advantages over a conventional op
amp inverting summing circuit. First, the inputs are both high
impedance and the circuit is noninverting. It would require
significant additional circuitry to make an op amp summing
circuit that has high input impedance and is noninverting.
Another advantage is that the AD8130 circuit still preserves the
full bandwidth of the part. In a conventional summing circuit,
the noise gain is increased for each additional input, so the
bandwidth response decreases accordingly. By this technique,
four signals can be summed by applying them to two AD8130s
and then summing the two outputs by a third AD8130.
CABLE-TAP AMPLIFIER
It is often desirable to have a video signal drive several pieces of
equipment. However, the cable should only be terminated once at
its endpoint; therefore, it is not appropriate to have a termination
at each device. A loop-through connection allows a device to tap
the video signal while not disturbing it by any excessive loading.
V1
Figure 141. Gain-of-2 Connections with No Resistors
V2
V
Figure 142. A Summing Circuit that is Noninverting
AD8130
IN
AD8130
4
5
1
8
8
4
5
1
with High Input Impedance
+
+
+
+
PD
3
PD
–V
–V
3
2
–V
S
–V
+V
2
+V
7
S
+V
S
+V
7
6
S
0.1 μ F
6
0.1 μ F
0.1 μ F
AD8129/AD8130
0.1 μ F
V
OUT
10 μ F
V
OUT
10 μ F
= V1 + V2
10 μ F
10 μ F