AD8027AR-REEL7 Analog Devices Inc, AD8027AR-REEL7 Datasheet - Page 18

• Manufacturer Part Number: AD8027AR-REEL7
• Description: IC OPAMP R-R LDIST LN LP 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8027AR-REEL7

• Rohs Status: RoHS non-compliant
• Amplifier Type: Voltage Feedback
• Number Of Circuits: 1
• Output Type: Rail-to-Rail
• Slew Rate: 100 V/µs
• -3db Bandwidth: 190MHz
• Current - Input Bias: 4µA
• Voltage - Input Offset: 200µV
• Current - Supply: 6.5mA
• Current - Output / Channel: 120mA
• Voltage - Supply, Single/dual (±): 2.7 V ~ 12 V, ±1.35 V ~ 6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Gain Bandwidth Product: -

AD8027/AD8028
In the event that the crossover region cannot be avoided,
specific attention has been given to the input stage to ensure
constant transconductance and minimal offset in all regions of
operation. The regions are PNP input pair running, NPN input
pair running, and both running at the same time (in the
200 mV crossover region). Maintaining constant transconduc-
tance in all regions ensures the best wideband distortion
performance when going between these regions. With this
technique, the AD8027/AD8028 can achieve greater than 80 dB
SFDR for a 2 V p-p, 1 MHz, and G = 1 signal on ±1.5 V
supplies. Another requirement needed to achieve this level of
distortion is that the offset of each pair must be laser trimmed
to achieve greater than 80 dB SFDR, even for low frequency
signals.
OUTPUT STAGE
The AD8027/AD8028 use a common-emitter output structure
to achieve rail-to-rail output capability. The output stage is
designed to drive 50 mA of linear output current, 40 mA within
200 mV of the rail, and 2.5 mA within 35 mV of the rail.
Loading of the output stage, including any possible feedback
network, lowers the open-loop gain of the amplifier. Refer to
Figure 49 for the loading behavior. Capacitive load can degrade
the phase margin of the amplifier. The AD8027/AD8028 can
drive up to 20 pF, G = 1, as shown in Figure 10. A small (25 Ω
to 50 Ω) series resistor, R
capacitive load is to exceed 20 pF for a gain of 1. Increasing the
closed-loop gain increases the amount of capacitive load that
can be driven before a series resistor needs to be included.
DC ERRORS
The AD8027/AD8028 use two complementary input stages to
achieve rail-to-rail input performance, as mentioned in the
Input Stage section. To use the dc performance over the entire
common-mode range, the input bias current and input offset
voltage of each pair must be considered.
Referring to Figure 56, the output offset voltage of each pair is
calculated by
where the difference of the two is the discontinuity experienced
when going through the crossover region.
V
V
OS
OS
,
,
PNP
NPN
,
,
OUT
OUT
=
=
V
V
OS
OS
,
,
SNUB
PNP
NPN
, should be included, if the
B
⎛
⎜
⎜
⎝
⎛
⎜
⎜
⎝
R
R
G
G
R
R
+
G
+
G
R
R
F
F
⎞
⎟
⎟
⎠
⎞
⎟
⎟
⎠
,
Rev. C | Page 18 of 24
The size of the discontinuity is defined as
Using the crossover select feature of the AD8027/AD8028 helps
to avoid this region. In the event that the region cannot be
avoided, the quantity (V
this effect.
Because the input pairs are complementary, the input bias cur-
rent reverses polarity when going through the crossover region
shown in Figure 37. The offset between pairs is described by
I
input pair is active, and I
input pair when the NPN pair is active. If R
when multiplied by the gain factor it equals R
eliminated. It is strongly recommended to balance the imped-
ances in this manner when traveling through the crossover
region to minimize the dc error and distortion. As an example,
assuming that the PNP input pair has an input bias current of
6 μA and the NPN input pair has an input bias current of
−2 μA, a 200 μV shift in offset occurs when traveling through
the crossover region with R
In addition to the input bias current shift between pairs, each
input pair has an input bias current offset that contributes to the
total offset in the following manner:
B, PNP
V
V
Δ
is the input bias current of either input when the PNP
OS,
DIS
V
OS
PNP
=
=
R
(
–
V
−
I
G
V
OS,
B
V
I
+
OS,
+
R
Figure 56. Op Amp DC Error Sources
PNP
NPN
S
+
⎛
⎜
⎜
⎝
R
V
R
OS
−
S
G
=
V
–
R
OS, PNP
I
I
(
B, NPN
OS,
+
B
B
I
G
+
–
B,
R
F
NPN
PNP
R
F
equal to 0 Ω and R
F
– V
is the input bias current of either
⎞
⎟
⎟
⎠
−
−
)
AD8027/
×
AD8028
I
OS, NPN
–
+
I
B
B,
⎛
⎜
⎜
⎝
−
R
NPN
R
+V
–V
G
) is trimmed to minimize
F
R
+
)
G
×
R
⎡
⎢
⎢
⎣
F
R
S
S
is sized so that
⎞
⎟
⎟
⎠
F
SELECT
⎛
⎜
⎜
⎝
, this effect is
R
S
G
equal to 25 Ω.
03327-A-055
R
+
+
V
G
OUT
R
F
–
⎞
⎟
⎟
⎠
−
R
F
⎤
⎥
⎥
⎦