MAX2036CCQ+T Maxim Integrated Products, MAX2036CCQ+T Datasheet - Page 16

• Manufacturer Part Number: MAX2036CCQ+T
• Description: IC VGA W/OCTAL MIXER 8CH 100TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX2036CCQ+T

• Amplifier Type: Variable Gain
• Number Of Circuits: 8
• Output Type: Differential
• -3db Bandwidth: 2MHz
• Current - Supply: 245mA
• Current - Output / Channel: 3.75mA
• Voltage - Supply, Single/dual (±): 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Slew Rate: -
• Gain Bandwidth Product: -
• Current - Input Bias: -
• Voltage - Input Offset: -

Ultrasound VGA Integrated
with CW Octal Mixer
The outputs from the octal mixer array are summed inter-
nally to produce the total CWD summed beamformed
signal. The octal array produces eight differential quad-
rature (Q) outputs and eight differential in-phase (I) out-
puts. All quadrature and in-phase outputs are summed
into single I and Q differential current outputs
(CW_QOUT+, CW_QOUT-, CW_IOUT+, CW_IOUT-).
The LO phase dividers can be programmed through
the shift registers to allow for 4, 8, or 16 quadrature
phases for a complete CW beamforming solution.
There are four separate modes of operating the CWD
beamformer. See Table 1 for a summary of the different
modes of operation. The mode of operation can be
selected by the CW_M1 and CW_M2 logic inputs.
Phase generation is controlled through the serial inter-
face. See the Serial Interface section in the Applications
Information section for details on how to program for
different quadrature phases.
For mode 1 operation, the LO_LVDS input frequency is
typically 16 x f
1MHz to 7.5MHz, the input frequency ranges from
16MHz to 120MHz. This high LO clock frequency
requires a differential LVDS input. The 16 x f
then divided by 16 to produce 16 phases. These 16
phases are generated for each of the 8 channels and
programmed for the selected phase by a serial shift
register. Each channel has a corresponding 5-bit shift
register, which is used to program the output phase of
Table 1. Summary of CWD Beamforming Methods
N/A = Not applicable.
16
CW_M1
0
0
1
1
______________________________________________________________________________________
CW_M2 MODE
0
1
0
1
LO
. As the CWD LO frequency range is
CW Mixer Output Summation
1
2
3
4
CWD Beamforming Modes
FREQUENCY
LO INPUT
16 x
8 x
4 x
4 x
LO Phase Select
INTERFACE
3V CMOS
3V CMOS
CLOCK
LVDS
LVDS
LO
Mode 1
input is
R ESO L U T IO N
Quadrature
16 phases
8 phases
4 phases
provided
PHASE
the divide-by-16 circuit. The first 4 bits of the shift regis-
ter are for programming the 16 phases; the fifth bit turns
each channel on/off individually. For mode 1, set both
CW_M1 and CW_M2 to a logic-low. See Table 2.
Table 2. Mode 1 Logic Table (B4 = 0:
Channel On/B4 = 1 Channel Off)
CW_M1 = 0
CW_M2 = 0
MODE 1
PHASE
(DEG)
112.5
157.5
202.5
247.5
292.5
337.5
22.5
67.5
135
180
225
270
315
45
90
0
PER CHIP
INPUTS
CLOCK
NO. OF
1
1
8
8
MSB
(B0)
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
BY SERIAL
PROGRAM
REGISTER
(B1)
SHIFT
(SSR)
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Yes
Yes
Yes
No
(B2)
B
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
USEFUL
BITS IN
NO. OF
SSR
N/A
LSB
(B3)
4
3
2
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SHUTDOWN
BITS IN
NO. OF
DON’T-
2 MSBs
1 MSB
CARE
(B4)
SD
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
SSR
N/A
0