AD745KR-16-REEL Analog Devices Inc, AD745KR-16-REEL Datasheet - Page 11
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AD745KR-16-REEL
Manufacturer Part Number
AD745KR-16-REEL
Description
IC OPAMP BIFET 20MHZ ULN 16SOIC
Manufacturer
Analog Devices Inc
Datasheet
1.AD745KRZ-16.pdf
(12 pages)
Specifications of AD745KR-16-REEL
Rohs Status
RoHS non-compliant
Amplifier Type
J-FET
Number Of Circuits
1
Slew Rate
12.5 V/µs
Gain Bandwidth Product
20MHz
-3db Bandwidth
20MHz
Current - Input Bias
150pA
Voltage - Input Offset
100µV
Current - Supply
8mA
Current - Output / Channel
40mA
Voltage - Supply, Single/dual (±)
9.6 V ~ 36 V, ±4.8 V ~ 18 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (0.300", 7.5mm Width)
Output Type
-
DESIGN CONSIDERATIONS FOR I-TO-V CONVERTERS
There are some simple rules of thumb when designing an I-V
converter where there is significant source capacitance (as with
a photodiode) and bandwidth needs to be optimized. Consider
the circuit of Figure 18. The high frequency noise gain
(1 + C
higher slew rate and bandwidth is ideally suited to this applica-
tion.
Here both the low current and low voltage noise of the AD745 can
be taken advantage of, since it is desirable in some instances to
have a large R
and, at the same time, operate the amplifier at high noise gain.
In this circuit, the R
width over which flat response can be obtained, in fact:
where:
With C
provide a two pole system with optimal flatness that has a corner
frequency of f
response. Note that bandwidth and sensitivity are directly traded
off against each other via the selection of R
photodiode with C
mum bandwidth of 360 kHz when capacitor C
Conversely, if only a 100 kHz bandwidth were required, then
the maximum value of R
tor C
In either case, the AD745 provides impedance transformation,
the effective transresistance, i.e., the I/V conversion gain, may
be augmented with further gain. A wideband low noise amplifier
such as the AD829 is recommended in this application.
This principle can also be used to apply the AD745 in a high
performance audio application. Figure 19 shows that an I-V
converter of a high performance DAC, here the AD1862, can
be designed to take advantage of the low voltage noise of the
AD745 (2.9 nV/ Hz) as well as the high slew rate and band-
width provided by decompensation. This circuit, with component
values shown, has a 12 dB/octave rolloff at 728 kHz, with a
passband ripple of less than 0.001 dB and a phase deviation of
less than 2 degrees @ 20 kHz.
f
f
B
C
f
B
= signal bandwidth
= gain bandwidth product of the amplifier
L
≈
S
still ≈ 4.5 pF.
L
/C
≈ 1/(2 π R
L
2π R
) is usually greater than five, so the AD745, with its
INPUT SOURCE: PHOTO DIODE,
B
f
F
. Capacitor C
C
F
ACCELEROMETER, ECT.
(which increases sensitivity to input current noise)
C
S
S
F
I
S
= 300 pF and R
F
C
C
S
) the net response can be adjusted to a
S
F
time constant limits the practical band-
would be 360 kΩ and that of capaci-
R
L
B
adjusts the damping of the circuit’s
C
S
F
= 100 kΩ will have a maxi-
AD745
C
R
F
L
F
. For example, a
L
≈ 4.5 pF.
An important feature of this circuit is that high frequency en-
ergy, such as clock feedthrough, is shunted to common via a
high quality capacitor and not the output stage of the amplifier,
greatly reducing the error signal at the input of the amplifier and
subsequent opportunities for intermodulation distortions.
BALANCING SOURCE IMPEDANCES
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD745. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier’s input capacitance and, as shown in Figure 20, noise
performance will be optimized. Figure 21 shows the required
external components for noninverting (A) and inverting (B)
configurations.
–12V
DIGITAL
0.01 F
INPUTS
+12V
–12V
0.01 F
40
30
20
10
0
10
0.01 F
1
2
3
4
5
6
7
8
BALANCED
CONVERTER
2.9nV/ Hz
20-BIT D/A
TOP VIEW
AD1862
3k
UNBALANCED
COMMON
DIGITAL
INPUT CAPACITANCE – pF
16
15
14
13
12
11
10
9
+12V
0.01 F
10 F
+
100
1 F
COMMON
ANALOG
+
2000pF
AD745
+12V
–12V
0.1 F
0.1 F
100pF
AD745
3 POLE
FILTER
PASS
LOW
1k
OUTPUT