AD8012AR-REEL7 Analog Devices Inc, AD8012AR-REEL7 Datasheet - Page 14

• Manufacturer Part Number: AD8012AR-REEL7
• Description: IC OPAMP CF DUAL LP 125MA 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8012AR-REEL7

• Rohs Status: RoHS non-compliant
• Amplifier Type: Current Feedback
• Number Of Circuits: 2
• Slew Rate: 2250 V/µs
• -3db Bandwidth: 350MHz
• Current - Input Bias: 3µA
• Voltage - Input Offset: 1500µV
• Current - Supply: 1.7mA
• Current - Output / Channel: 125mA
• Voltage - Supply, Single/dual (±): 3 V ~ 12 V, ±1.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Power Supply Requirement: Single/Dual
• Package Type: SOIC N
• Pin Count: 8
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / Rohs Status: Not Compliant

AD8012
Choosing the Appropriate Turns Ratio for the Transformer
Increasing the peak-to-peak output signal of the amplifier in the
previous example and adding a variation in the turns ratio of the
transformer can yield further enhancements to the circuit. The
output signal swing of the AD8012 can be increased to about
± 3.9 V before clipping occurs. This increases the peak-to-peak
output of the differential amplifier to 15.6 V. Because the signal
applied to the primary winding is now bigger, the transformer
turns ratio of 1:1 can be replaced with a (step-down) turns ratio
of about 1.3:1 (from amplifier to line). This steps the 7.8 V
peak-to-peak primary voltage down to 6 V. This is the same
secondary voltage of the earlier examples, so the resulting power
delivered to the line is the same.
The received signal, which is small relative to the transmitted
signal, will, however, be stepped up by a factor of 1.3. Amplifying
the received signal in this manner enhances its signal-to-noise
ratio and is useful when the received signal is small compared to
the to-be-transmitted signal.
The impedance reflected from the 135 Ω line now becomes
228 Ω (1.3
amplifier must now drive a total load of 456 Ω (114 Ω + 114 Ω
+ 228 Ω), considerably more than the original 270 Ω load. This
reduces the drive current from the op amps by about 40%.
More significant, however, is the reduction in dynamic power
consumption—that is, the power the amplifier must consume in
order to deliver the load power. Increasing the output signal so
that it is as close as possible to the power rails minimizes the
power consumed in the amplifier.
There is, however, a price to pay in terms of increased signal
distortion. Increasing the output signal of each op amp from the
original ± 3 V to ± 3.9 V reduces the spurious-free dynamic
range (SFDR) from –65 dB to –50 dB (measured at 500 kHz),
even though the overall load impedance has increased from
270 Ω to 456 Ω.
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8012 requires
careful attention to board layout and component selection.
Table I shows recommended component values for the AD8012
and Figures 8–13 show recommended layouts for the 8-lead
SOIC and MSOP packages for a positive gain. Proper RF
design techniques and low parasitic component selections
are mandatory.
2
135 Ω). With a correctly terminated line, the
Gain
–1
+1
+2
+10
R
T
chosen for 50 Ω characteristic input impedance.
R
750 Ω
750 Ω
750 Ω
750 Ω
F
Table I. Typical Bandwidth vs. Gain Setting Resistors
R
750 Ω
750 Ω
82.5 Ω
G
–14–
R
53.6 Ω
49.9 Ω
49.9 Ω
49.9 Ω
T
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Figure 7).
One end should be connected to the ground plane and the other
within 1/8 inch of each power pin. An additional (4.7 µF to 10 µF)
tantalum electrolytic capacitor should be connected in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to
a minimum. Capacitance greater than 1.5 pF at the inverting
input will significantly affect high speed performance when
operating at low noninverting gains.
Stripline design techniques should be used for long signal traces
(greater than about 1 inch). They should be designed with the
proper system characteristic impedance and be properly termi-
nated at each end.
Figure 7. Inverting and Noninverting Configurations
V
IN
V
IN
*R
*R
R
O
O
Small Signal –3 dB BW (MHz),
V
110
350
150
40
G
R
R
CHOSEN FOR CHARACTERISTIC IMPEDANCE.
CHOSEN FOR CHARACTERISTIC IMPEDANCE.
S
T
G
= 5 V, R
NONINVERTING CONFIGURATION
R
T
INVERTING CONFIGURATION
+V
L
–V
= 1 k
S
R
R
S
F
F
0.1 F
10 F
0.1 F
+
10 F
+
R
R
O
O
*
*
V
V
OUT
OUT
REV. B